Several techniques can be used to reduce power consumption. Implementing required functionality efficiently is fundamental as this reduces the area. As geometry shrinks,
Leakage power becomes significant because Vt also scales down. In standby mode leakage power dominates. Therefore in standby mode - power gating, or back-biasing can be used.
Using different voltages is another technique but voltage shifters have to be used. Non-critical logic is run on lower voltage.
Or non-critical logic can use higher Vt. But difficult from a process point of view. No voltage shifters needed.
There is a new technique called gate-biasing but uses extra transistors.
Dynamic:
clock-gating is a popular technique used to reduce dynamic power. Other techniques include operand-isolation, rearranging inputs to reduce switching activity(set_max_dynamic_power), using gray-coding for FSM states and FIFO pointers, balancing delay in logic to avoid glitches in output.
Switching activity on datapath depends on throughput and probability next word will be different from current word. Incresing clock frequency decreases switching activity proportionally but since clock-tree typically consumes 30% of the power( because of high capacitance and high switching activity) so increasing frequency will increase power consumption though not proportionally.
A good ee design article on low-power techniques.