I have so far worked on 3 ASICs. All the three are in Networking. I have a strong digital design with Networking background as a result of course work and experience.
Design
I have Strong Verilog RTL design experience. I had used VHDL but i have primarily been using Verilog at work. Very quick concept to RTL designer. Strong logic design background including FSMs, combinational logic, asynchronous interfaces, low-power and high-speed design. Responsible for design and verification of several blocks. In some cases i had to come up with specifications for the module myself after researching white papers and publications.
Bus Architecture and Embedded processor
Directly worked on PCI, PCMCIA, and Ethernet. Familiar with USB, PCI Express and ARM processor. Decided which ARM processor to use after considering the pros and cons. Did the bus architecture for UWB MAC to maximize performance and throughput and meet timing.
Verification
I was responsible for the verification of blocks i designed. Confident in coming up with a list of testcases to thoroughly verify a block. Took part in creation of test benches and task calls. Experience with the flow to certify RTL as 100% verified. I have knowledge of Specman & have proficiency in e languge. Experience in creating random testcases and bus functional models in verilog, running regression. Experience with tools: VCS, VirSim, ModelSim, SureCov.
Good at converting simulation testvectors to tester(manufacturing testvectors). Exposure to assertions.
FPGAs and Lab debug
I have experience with FPGA synthesis and place & route tools. I did emulation using Altera FPGAs which involved converting Verilog RTL from ASIC to FPGA. I was involved in Lab debug and bring-up involving use of Logic Analyzers, Oscilloscopes, running testcases on boards, knowledge of Lab safety and other equipment.
Synthesis and other back-end tools
I have written scripts in Synopsys Design Compiler to perform module level and toplevel synthesis. I also have experience with performing Static Timing Analysis using Primetime.
I used PowerCompiler and PrimePower to perform power estimation.
Networking Protocols
MAC layer, Ethernet, wireless LAN(802.11), TCP/IP, Ultra Wideband(802.15), ATM. Strong networking system design background. Influenced the system design of UWB MAC. Came up with algorithms to manage frames efficiently.
Architecture
Familiar with MAC architecture and Switch-Fabric architecture. Did the hardware architecture for UWB MAC and influenced hardware-software partitioning of functions in UWB MAC.
UNIX and Perl
Used UNIX environment for past 5 years. Good with Perl.