All ARM processors are based on RISC architecture.
The ARM7 is a now older processor. It is a 3-stage pipeline processor. Both instructions and data are stored in the same memory. The memory cycle should be finished by 1 clock cycle if NO wait states have to be inserted. Inserting wait states reduces performance of the processor. In "pipelined" mode, the processor asserts request signal 1 cycle ahead and address is provided 0.5 cycle ahead of usual timing. In "pipelined" mode, effictively there are 2 clock cycles to complete memory cycle without affecting performance(without inserting wait state). Fast RAMs that enable memory accesses to complete without inserting wait states are called zero wait state(ZWS) RAMs.
The ARM9 uses 5-stage pipeline and therefore can run at higher clock rate than ARM7. It uses seperate instruction and data memory so that probability that consecutive instructions trying to access memory at the same time is reduced. This removes memory access from being the bottleneck. Eventhough ARM9 consumes more power than ARM7, it consumes less power per instruction than ARM7. The cache controller is standardised for ARM9 but is proprietary for ARM7.
The AMBA bus is a standardised bus system defined by ARM. ARM does not provide the implementation but the vendors do. The AMBA bus was defined to provide a standard solution for ARM interface so that each team does not design one of its own. The AMBA specification defines AHB, AHB-lite, ASB, APB buses. The AMBA bus uses a pipelined address, data phase to keep bus busy every clock cycle and provide ZWS access. To hook-up processor to AMBA bus, the processor has to be put in "pipelined" mode in the case of ARM7..