BIOS Settings - Advanced Chipset Features



This section of the BIOS setup program provides settings to 
"tweak" the chipset control parameters. Most of these settings 
are associated with fine-tuning control over the system cache, 
memory, and I/O buses, to optimize performance.

	Warning: This section contains many settings that have 
the potential to screw up your system. :^) If after reading 
these descriptions you are not sure what a setting does, it is 
usually best to leave it at its default setting. For most people, 
using some form of the automatic configuration setting is 
highly recommended.


Chipset Special Features / Global Features

Some chipsets have this "generic" setting that, when enabled, 
turns on some of the special performance-enhancing features of 
the chipset. This should normally be enabled unless you 
experience lockups or other system problems.

I have thus far only encountered this setting on motherboards 
that use Intel's 430HX "Triton II" chipset .


Cache Timing

This setting determines the speed that the chipset will use for 
reading data from the external (level 2) cache. This normally 
appears as something like x-y-y-y. In this case the parameter 
refers to the number of clock cycles to do a 32-byte burst read 
from the external cache line. Each entry in the cache of a modern 
PC is 256 bits wide; data is read from the cache using four 
consecutive 64-bit reads. The first read is normally slower than 
the others; this is the "x" above, and the next three reads are 
the "y"s. An example would be "3-1-1-1", which means it takes a 
total of six clock cycles to read from the cache. More 
information on cache timing can be found here .

In general, the lower these numbers, the faster your system will 
be. How low you can drop them depends on your system, how fast 
your memory is, what clock speed your memory bus runs at, etc. 
If your BIOS supports an "Auto" setting for this parameter, 
using it is normally wisest, although it may not produce the 
highest performance results. You can try more aggressive 
settings (lower numbers) but be prepared to back off if you 
experience system problems, and don't go below the rating for 
your cache type.


Level 2 Cacheable DRAM Size / Cache Over 64 MB of DRAM

This setting controls how much of the system memory is "covered" 
by the level 2 cache. Using uncached memory on your system can 
cause it to slow down dramatically . You should always ensure 
that this value is set at least as high as the total amount of 
RAM in your system. However, for best performance, do not set 
it any higher than it needs to be.

Many motherboards using the 430FX, 430VX and 430TX chipsets will 
not have this option; it is most common on 430HX motherboards to 
select between 64 MB and 512 MB cacheability. You should in this 
case set it to 64 MB unless you are using more than 64 MB.

	Note: This setting will not be present on Pentium Pro 
motherboards, since the Pentium Pro uses an integrated level 
2 cache.


Level 2 Cache Size

Some systems have a specific setting you must change to indicate 
how much level 2 cache you have on your board. Most newer boards 
do not have this setting and instead the hardware automatically 
detects how much level 2 cache you have. If you have this setting 
in your setup program, make sure 
it is correct.

	Note: This setting will not be present on Pentium Pro or 
Pentium II motherboards, since these chips use integrated level 
2 cache, not cache on the motherboard.


System BIOS Cacheable

On most systems, you can shadow your system BIOS ROM . Shadowing 
increases performance by copying the BIOS code from ROM to much 
faster system RAM. Enabling this setting will allow the system 
to cache this RAM as well, further increasing performance.

Normally you will want to enable this unless you are having a 
problem with your system and turning it off fixes it. If you have 
system BIOS shadowing disabled, this setting will be ignored.


Video BIOS Cacheable

On most systems, you can shadow your system BIOS ROM . Shadowing 
increases performance by copying the video BIOS code from video 
adapter's ROM to much faster system RAM. Enabling this setting 
will allow the system to cache this RAM as well, further 
increasing performance.

Normally you will want to enable this unless you are having a 
problem with your system and turning it off fixes it. If you 
have video BIOS shadowing disabled, this setting will be ignored.


DRAM Parity Checking

When enabled, turns on parity checking for the system RAM. This 
should be enabled if you are using parity checking (or ECC), and 
disabled otherwise. The default is normally "Disabled" since 
(unfortunately) most modern systems don't use parity memory. I 
recommend the use of parity memory; see here for details on what 
parity memory is , and see here for a discussion of the merits 
of parity memory versus non-parity memory .

	Warning: If you turn on parity checking on a system that 
does not have parity memory in it, the system will halt with a 
parity error as soon as it tries to boot up. If you turn off 
parity checking on a system that does have parity memory, the 
system will run just fine, but you will have no parity checking 
protection active.


DRAM Parity / ECC Mode

On a system that supports both parity and ECC error 
detection / correction modes--most newer systems support either 
both or neither--selects which mode is activated. ECC stands for 
"error correcting code" or "error correction code" and is a more 
advanced error detection and correction protocol than 
straight parity.

The default for this setting is normally "Parity"; it is ignored 
or disabled if "DRAM Parity Checking" is disabled.


Single Bit Error Report

If you are enabling ECC on your system, the hardware is capable 
of detecting and correcting single-bit errors on the fly. It is 
very useful to be able to know when this has happened, because 
if it happens often then this is a signal that you have a 
hardware or software problem in your PC. Enabling this option 
will cause the system to tell you when it corrects a single-bit 
error when ECC is running. The default is usually "Disabled". I 
recommend enabling this if you are running with ECC enabled.


DRAM Speed / DRAM Timing / DRAM Auto Configuration

There are a number of settings that control the timing of your 
system memory. For a full discussion on system memory timing, 
look here. Most setup programs now come with some sort of 
"automatic" setting that will determine what these parameters 
are for you. This is a "parent" setting of sorts that can be 
used to control the other individual timing settings on the 
screen. These parent settings normally come in one of 
two flavors: 

Dynamic Automatic Timing Setting: Some BIOSes have a fully 
automatic setting. When you put the DRAM Timing setting on 
"Auto", the chipset will detect what type of memory and cache 
you have at boot time and dynamically set all the timings for 
you automatically based on what it finds. This is the simplest 
way to ensure basically good performance from your system using 
any type of memory that it supports. 

Fixed Timing Based on Memory Speed: Other BIOSes, instead of 
having an "Auto" setting, let you choose from a selection of 
common memory speeds (or types) and then modify the individual 
timing settings based on your selection. Here, you may find 
settings like "70 ns", "60 ns", "EDO" and "Manual". "Manual" 
turns off the automated settings so you can tweak them yourself. 

When you use the "Auto" setting (either fully automatic or by 
selecting a memory speed) the BIOS will normally "lock" the 
individual settings that are controlled by this one, to reflect 
the fact that they are being set automatically by the BIOS. To 
unlock the individual settings so you can change them, you 
normally must turn off the "Auto" setting, or select "Manual". 
The default in most BIOSes is to enable automatic 
timing settings.

	Warning: In a system that dynamically sets timing based 
on the detected speed of your memory, you must take care when 
using memory of different speeds . You should generally put the 
slower memory in the first bank, often called Bank 0. Otherwise, 
the system may set the timing too fast for the slower chips.


DRAM R/W Leadoff Timing

This parameter controls how many clock cycles are required for 
the first access to memory during a four-read "burst". In modern 
PCs, reads from the system memory are done in sets of four, 
because the level 2 cache used in the PC (which is filled by 
information from the main memory) is 256 bits wide (four sets of 
64 bits). The timing, in clock cycles, to perform this quadruple 
read is normally stated as "x-y-y-y". The first read is slower 
because the address for the read must be supplied to the memory; 
the next three are faster because they are read consecutively 
from the first location (no need to supply an address). Memory 
system timing is discussed in much more detail here .

Using the x-y-y-y notation, the Leadoff Timing setting refers to 
the "x" value, the number of clock cycles for the first read. On 
most BIOSes, this parameter is absolute, and refers to the actual 
number of clock cycles used for the first access. On others, this 
setting is the number of additional cycles required for the first 
access. For example, let's suppose the optimal burst timing for 
your system is 5-2-2-2. This means the first read takes 5 clock 
cycles, and the next three take 2 each. In most BIOSes, Leadoff 
Timing would here be set to 5. In some BIOSes, you would have a 
parameter called "Leadoff Wait States" or "Additional Leadoff 
Cycles", and you would put here 3 (the number of additional 
cycles required for the first read.)

The lower this setting, the faster your system will work. How low 
you can set this depends on your memory bus speed and the speed 
and type of memory you are using. In general, the faster your 
memory bus runs the more cycles it will take to access the 
memory unless the memory is also made faster. Putting this 
setting too low will cause memory errors; some of these can 
appear intermittently and be very difficult to diagnose. Using 
automatic timing to set this parameter is usually recommended.

By default most BIOSes enable automatic timing settings so this 
parameter would be "locked out" and not changeable; if you 
enable manual timing settings this setting will usually default 
to the slowest possible setting at first, 
for compatibility reasons.

	Note: This setting controls the timing for both reads 
and writes. Some systems could have two different settings 
instead, one for read leadoff timing and the other for write 
leadoff timing.

	Note: This setting is normally controlled by the DRAM 
Timing or Auto Configuration mode, and if automatic settings are 
enabled you may not be able to change this.


DRAM Read Timing / DRAM Burst Read Timing / DRAM Read Wait States

This parameter controls how many clock cycles are required for 
the burst reads from memory during a four-read "burst". In most 
modern PCs, reads from the system memory are done in sets of four, 
because the level 2 cache used in the PC (which is filled by 
information from the main memory) is 256 bits wide (four sets of 
64 bits). The timing, in clock cycles, to perform this quadruple 
read is normally stated as "x-y-y-y". The first read is slower 
because the address for the read must be supplied to the memory; 
the next three are faster because they are read consecutively 
from the addresses immediately following the first location (no 
need to supply an address). Memory system timing is discussed in 
much more detail here .

Using the x-y-y-y notation, the Read Timing or Burst Read Timing 
setting refers to the "y-y-y" value, the number of clock cycles 
for the 2nd, 3rd and 4th reads of the four-read cycle. This 
setting will most often have options like "x-2-2-2", "x-3-3-3" 
and "x-4-4-4", although in some BIOSes the single number is used 
instead ("2", "3", "4".) Some BIOSes, especially on older 
machines, instead refer to read "wait states", which is 
essentially the same thing, except that it is one less than the 
number referred to above. A wait state is an extra cycle inserted 
for the processor to wait for the system memory. In the x-y-y-y 
notation, the "y" is the total number of cycles for each memory 
access. "x-1-1-1" is the best you can do, since it always takes 
at least one cycle. Zero wait states is the best you can do. 
So "x-3-3-3" is equivalent to 2 wait states. 

Some chipsets will have a double value for this setting, with one 
used for EDO DRAM and another used for FPM DRAM. The system 
automatically detects which is being used; this is a sort of 
"semi-automatic" setting. In this case you may see options that 
look something like "x-2-2-2 / x-3-3-3" or "x-3-3-3 / x-4-4-4-4". 
The first timing number is used when EDO is detected and the 
second when FPM is detected. Your system will operate fastest 
when this setting is as low as possible. How low you can set 
this depends on your memory bus speed and the speed and type of 
memory you are using. In general, the faster your memory bus 
runs the more cycles it will take to access the memory unless 
the memory is also made faster. Putting this setting too low 
will cause memory errors; some of these can appear intermittently 
and be very difficult to diagnose. Using automatic timing to set 
this parameter is usually recommended.

By default most BIOSes enable automatic timing settings so this 
parameter would be "locked out" and not changeable; if you 
enable manual timing settings this setting will usually default 
to the slowest possible setting at first, for compatibility reasons.

	Note: This setting is normally controlled by the DRAM 
Timing or Auto Configuration mode, and if automatic settings are 
enabled you may not be able to change this.

	Note: On some BIOSes this setting is combined with DRAM 
Write Timing / DRAM Write Burst Timing. In this case the same 
timing is used for both reads and writes.


DRAM Write Timing / DRAM Burst Write Timing / DRAM Write 
Wait States

This parameter controls how many clock cycles are required for 
the burst writes to memory during a four-read "burst". In most 
modern PCs, writes to the system memory are done in sets of four, 
because the level 2 cache used in the PC (which is filled by 
information from the main memory) is 256 bits wide (four sets of 
64 bits). The timing, in clock cycles, to perform this quadruple 
write is normally stated as "x-y-y-y". The first write is slower 
because the address for the write must be supplied to the memory; 
the next three are faster because they are written consecutively 
to the addresses immediately following the first location (no 
need to supply an address). Memory system timing is discussed 
in much more detail here .

Using the x-y-y-y notation, the Write Timing or Burst Write 
Timing setting refers to the "y-y-y" value, the number of clock 
cycles for the 2nd, 3rd and 4th writes of the four-write cycle. 
This setting will most often have options like "x-2-2-2", 
"x-3-3-3" and "x-4-4-4", although in some BIOSes the single 
number is used instead ("2", "3", "4".) Some BIOSes, especially 
on older machines, instead refer to write "wait states", which 
is 
essentially the same thing, except that it is one less than the 
number referred to above. A wait state is an extra cycle inserted 
for the processor to wait for the system memory. In the x-y-y-y 
notation, the "y" is the total number of cycles. "x-1-1-1" is the 
best you can do, since it always takes at least one cycle. Zero 
wait states is the best you can do. So "x-3-3-3" is equivalent 
to 2 wait states.

	Note: Systems that have a double value for read burst 
timing (one for EDO memory and one for FPM ) will still have just 
a single value for write burst timing. This is because EDO is 
only faster than FPM memory when reading.

Your system will operate fastest when this setting is as low as 
possible. How low you can set this depends on your memory bus 
speed and the speed and type of memory you are using. In general, 
the faster your memory bus runs the more cycles it will take to 
access the memory unless the memory is also made faster. Putting 
this setting too low will cause memory errors; some of these can 
appear intermittently and be very difficult to diagnose. Using 
automatic timing to set this parameter is usually recommended. 
By default most BIOSes enable automatic timing settings so this 
parameter would be "locked out" and not changeable; if you enable 
manual timing settings this setting will usually default to the 
slowest possible setting at first, for compatibility reasons.

	Note: This setting is normally controlled by the DRAM 
Timing or Auto Configuration mode, and if automatic settings are 
enabled you may not be able to change this.

	Note: On some BIOSes this setting is combined with DRAM 
Read Timing / DRAM Read Burst Timing. In this case the same 
timing is used for both reads and writes.


DRAM Speculative Leadoff

This is a performance enhancement available with some chipsets to 
speed up the (relatively slow) first access to system memory. In 
short, the memory controller "cheats" by starting the initial 
read request before the address for the read has been completely 
resolved. This can result in a performance increase. For best 
efficiency you will normally enable this. If doing so causes 
instability then you should disable it.

	Note: This setting is normally controlled by the DRAM 
Timing or Auto Configuration mode, and if automatic settings are 
enabled you may not be able to change this.


Turn-Around Insertion

When enabled, inserts an extra clock cycle (wait state) between 
consecutive DRAM read cycles (i.e., consecutive 4-read bursts). 
Normally the system can perform back-to-back burst reads without 
this extra delay, and the default for this setting is "Disabled".

	Note: This setting is normally controlled by the DRAM 
Timing or Auto Configuration mode, and if automatic settings 
are enabled you may not be able to change this.


Memory Hole

Some (unusual) expansion cards require access to particular 
memory addresses in order to function properly. This parameter 
lets you set aside the appropriate area of memory for these 
cards. The typical memory areas that can be set aside are 
"512-640KB" (the upper 128K of conventional memory) 
and "15-16MB".

This setting should be disabled unless you have a card that you 
know requires this setting. The default is normally "Disabled".


ISA (or AT Bus) Clock Speed / Divisor

This setting controls the speed of the ISA bus, in one of two 
ways. The less common way is for the setting to allow a direct 
setting of the ISA clock speed; this would include options of 
"6 MHz", "8 MHz", etc. The most common way is for the ISA clock 
speed to be set as a fraction of the PCI clock speed. The 
settings in this case will usually look something like 
"PCICLK/3", "PCICLK/4", "PCICLK/6", etc.

The setting to choose is the one that puts the ISA clock speed 
as close as possible to 8.33 MHz, which is the accepted 
standard maximum clock speed for the bus. Anything higher than 
this is considered overclocking. 8.33 MHz means that the 
correct option for a 33 MHz or 30 MHz PCI machine would be 
"PCICLK/4", while for a 25 MHz PCI machine it would be "PCICLK/3".

On some BIOSes there is an "Auto" setting as well that will pick 
the right fraction depending on the PCI bus speed it detects, but 
this is somewhat less common in my experience than other 
automatic settings elsewhere in the BIOS.


8-Bit I/O Recovery Time

This setting allows you to insert additional clock cycles after 
an 8-bit ISA I/O request. These are sometimes needed to slow 
down the processor after completing activity on the ISA bus, 
which runs much slower than the PCI bus. The default setting for 
this is usually 1 cycle. This can normally be increased to 5 or 
higher, or reduced to 0 (disabled). Normally you will want to 
keep this at its default setting. 


16-Bit I/O Recovery Time

This setting allows you to insert additional clock cycles after a 
16-bit ISA I/O request. These are sometimes needed to slow down 
the processor after completing activity on the ISA bus, which 
runs much slower than the PCI bus. The default setting for this 
is usually 1 cycle. This can normally be increased to 5 or 
higher, or reduced to 0 (disabled). Normally you will want to 
keep this at its default setting. 


Peer Concurrency

This setting, when enabled, allows multiple PCI devices to be 
active at the same time. The default for this setting is 
"Enabled" and you will normally want to leave it on the default.
