Chapter 8: Finite Automata with Output

Topics
The Mealy machine
The Moore machine
Moore = Mealy
An incrementer
Transducers as models of sequential circuits



A FA has two behaviors: accept or reject.

We now modify an FA so it will produce "output".  Such abstract machines are often referred to as transducers. There are two well-understood types of transducers, as follows.


The Mealy machine

Start with an ordinary FA, but remove final states:

For each transition, also specify a character to be "output" when the transition is taken:

For this mealy machine, the output vocabulary consists of 0’s or 1’s; they could be anything.

Run the machine:   input: aab             output: 101


The Moore machine

Again, start with a FA without final states, but specify a character to be output whenever a state (including the start state) is entered:

Run the machine:        input: aab         output: xyyz


Moore = Mealy

Q: Can we construct a Mealy machine that has the same input/output behavior as a given Moore machine (assuming that we ignore the first character of the Moore machine, which is always the same), and vice-versa? In other words, does Moore = Mealy ?

A: Yes, and it’s not too hard to prove (see the book)


An Incrementer

Here's an example of a Mealy machine that does something useful:

input: a binary number (in reverse order) e.g. 1011 (read in reverse order = 1310)
output: if you reverse it, you get (reversed input) + 1

Run it on 1011:
 

state input output
C 1 0
C 0 1
N 1 1
N 1 1

Reverse of output: 1110 = 1410  !!


Transducers as models of sequential circuits

We know that "real" computers are not abstract automata; they are built out of "hardware" components:

Let’s look at the following "hardware" circuit, and see how it relates to a FA with output:

1.  AND, XOR and DELAY are readily available hardware components:
 
AND its output becomes the logical "and" of its two inputs: 1 iff both inputs are 1
XOR its output becomes the logical "exclusive or" of its two inputs 0 iff both inputs are the same
DELAY delays its input by one clock cycle

2.  input: each clock cycle, it will be either a 0 or a 1
3.  output: each clock cycle, 0 or 1
4.  we can arrange that, initially, there will be a 1 on wire S as shown

We define the "state" of this machine to be "carry" if the value on "wire S" is 1, "no carry", otherwise. The reason for these names will soon become evident. Clearly, our machine will have only two states, and will start in state "carry".  A new state will be computed on each clock cycle as a result of the circuitry.

Now, let’s describe the Mealy-machine behavior of our hardware machine:


 
input
 
1
0
old state new state output new state output
carry carry 0 no carry 1
no carry no carry 1 no carry 0

Schematically:

The hardware circuit implements the "incrementer" FA!

A larger circuit (with more delays) will have states which depend on values on more wires; hence more states. But the analysis of the circuit will be the same.

Synthesis: putting a circuit together from the FA description, is deferred to another course!

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