In many situations, the indirect techniques for performing subtraction and negation operations are undesirable. These indirect techniques often require an undesirably large amount of circuit area or number of components for their implementation. Moreover, these indirect techniques often cause the propagation delay between the time when an incoming number is valid and the time when the subtraction or negation operation results are valid to be undesirably long.
SUMMARY OF THE INVENTION
Accordingly, it is an advantage of the present invention that an improved arithmetic circuit is provided. Another advantage of the present invention is that an arithmetic circuit is provided which may be incorporated in a wide variety of applications, including arithmetic logic units (ALUs) for microprocessors or other computing circuits, add/subtract circuits, subtraction circuits, and negation circuits.
Another advantage of the present invention is that an arithmetic circuit is provided which generates a two's complement negation of an incoming number in a small amount of space and with a small amount of propagation delay.
Another advantage of the present invention is that and arithmetic circuit is provided which selectively generates a negation of an incoming number.
Another advantage of the present invention is that and arithmetic circuit is provided which selectively performs addition or subtraction operations, wherein the subtraction operations are perforned in a direct manner which does not require the generation of a carry input pulse.
Another advantage of the present invention is that and arithmetic circuit is provided which may be adapted to efficiently generate negations for incoming numbers having any number of bits.
CONFIRMATION AVAILABLE:
Law Office of R. MICHAEL WEST
A Professional Corporation
455 Capitol Mall, Suite 405
Sacramento, California 95814
916-444-5444
FACSIMILE 916-444-5441
E-mail [email protected]
I look forward to hearing from you soon.
Kindest personal regards.
Sincerely,
JR. Gilber't
Post Office Box 36832
Tucson, Arizona 85740
US Patent and Trademark Office
PN: 5,333,120
$20,000,000 Persons to confirm Microchip
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Dear, Sir/Madam:
Infurtherance please view!
I have spent years in college as a Graduate, and a student colleague of a prominent known Scientist and dear personal friend. Dr. Rastko C. Maglic is the father creator of the Operational Amplifier. Dr. Maglic classified and peered JR as a higher intellect and being a Scientist in his own rights as the inventor of Selective Negation. The inventor's technology was tested beyond 64 bit Technology, and honored by the National Institute of Standards and Technology. It describes a novel binary adder that is faster than conventional adders. This included advantages over competing products or processes on the market or in development.
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to digital electronic circuits, such as those used in general purpose computers and microprocessors and in special purpose machines. More specifically, the present invention relates to electronic circuits which are used in performing arithmetic operations on two's complement binary numbers.
BACKROUND OF THE INVENTION
Conventional binary arithmetic circuits perform arithmetic operations, particularly subtraction and negation, in an indirect and inefficient manner. Subtraction has been performed by inverting a subtrahend number to form a one's complement of the subtrahend, adding the inverted subtrahend to a minuend number, and then incrementing the addition result. The incrementing of the addition result is typically accomplished by supplying a carry pulse to an adder when a subtraction is performed. A simple negation has been treated as a special subtraction problem with the minuend forced to equal zero.
