By the late 1980s, the proliferation of 32-bit CPUs and graphics-intensive operating systems made it painfully obvious that the 8.33MHz ISA bus was no longer satisfactory. The PC industry began to develop alternative architectures for improved performance. Two architectures are now prominent; VL and PCI. While the VL bus seems ideal, there are some serious limitations that must be overcome. Perhaps most important is the VL bus dependence on CPU speed - fast computers must use wait states with the VL bus, and only supports 1 or 2 slots maximum. Another problem is that the VL standard is voluntary, and not all manufacturers adhere to VESA specifications completely. In mid-1992, Intel Corporation and a comprehensive consortium of manufacturers introduced the Peripheral Component Interconnect (PCI) bus. Where the VL bus was designed specifically to enhance PC video systems, the 188 pin PCI bus looks to the future of CPUs (and PCs in general) by providing a bus architecture that also supports peripherals such as hard drives, networks, and so on. This chapter shows you the layout and operations of the PCI bus.

The PCI architecture is capable of transferring data at 132MB/sec - a great improvement over the 5MB/sec transfer rate of the standard ISA bus. Another key advantage of the PCI bus is that it

will have automatic configuration capabilities for switchless/jumperless peripherals. Auto-configuration (the heart of "plug-and-play") will take care of all addresses, interrupt request, and DMA used by a PCI peripheral. Table 39-1 lists the features for a PCI bus.

The PCI bus supports linear bursts, which is a method of transferring data that insures the bus is continually filled with data. The peripheral devices expect to receive data from the system main

memory in a linear address order, this means that large amounts of data is read from or written to a single address, which is then incremented for the next byte in the stream. The linear burst is one of the unique aspects of the PCI bus since it will perform both burst reads and burst writes. In short, it will transfer data on the bus every clock cycle - this doubles the PCI throughput compared to buses without linear burst capabilities.

The devices designed to support PCI have low access latency, reducing the time required for a peripheral to be granted control of the bus after requesting access. For example, an Ethernet

controller card connected to a LAN has large data files from the network coming into its buffer. Waiting for access to the bus, the Ethernet is unable to transfer the data to the CPU quickly enough to avoid a buffer overflow - forcing it to temporarily store the file's contents in extra RAM. Since PCI-compliant devices support faster access times, the Ethernet card can promptly send data to the CPU.

The PCI bus supports bus mastering, which allows one of a number of intelligent peripherals to take control of the bus in order to accelerate a high-throughput, high-priority task. PCI architecture also supports concurrency - a technique that ensures the microprocessor operates simultaneously with these masters, instead of waiting for them. As one example, concurrency allows the CPU to perform floating-point calculations on a spreadsheet while an Ethernet card and the LAN have control of the bus. Finally, PCI was developed as a dual-voltage architecture. Normally, the bus is a +5Vdc system like other busses. However, the bus can also operate in a +3.3Vdc (low-voltage) mode.

The layout for a PCI bus slot is shown in Fig. 39-1. Note that there are two major segments to the +5Vdc-version connector. A +3.3Vdc-version connector adds a key in the 12/13 positions to prevent accidental insertion of a +5Vdc PCI board into a +3.3Vdc slot. Similarly, the +5Vdc slot is keyed in the 50/51 position to prevent placing a +3.3Vdc board into a +5Vdc slot. The pinout for a PCI bus is shown in Table 39-2.

To reduce the number of pins needed in the PCI bus, data and address lines are multiplexed together (Adr./Dat 0 to Adr./Dat 63). It is also interesting to note that PCI is the first bus standard designed to support a low-voltage (+3.3 Vdc) logic implementation. On inspection, you will see that +5 Vdc and +3.3 Vdc implementations of the PCI bus place their physical key slots in different places so that the two implementations are not interchangeable. The Clock (CLOCK) signal provides timing for the PCI bus only, and can be adjusted from DC (0Hz) to 33MHz. Asserting the -Reset (-RST) signal will reset all PCI devices. Since the 64 bit data path uses eight bytes, the Command/ -Byte Enable signals (C/ -BE0 to C/ -BE7) define which bytes are transferred. Parity across the Address/Data and Byte Enable lines is represented with a Parity (PAR) or 64 Bit Parity (PAR64) signal. Bus mastering is initiated by the -Request (-REQ) line and granted after approval using the -Grant (-GNT) line.

When a valid PCI bus cycle is in progress, the -Frame (-FRAME) signal is true. If the PCI bus cycle is in its final phase, -Frame will be released. The -Target Ready (-TRDY) line is true when an addressed device is able to complete the data phase of its bus cycle. An -Initiator Ready (-IRDY) signal indicates that valid data is present on the bus (or the bus is ready to accept data). The -FRAME, -TARGET READY, and -INITIATOR READY signals are all used together. A -Stop (-STOP) signal is asserted by a target asking a master to halt the current data transfer. The ID Select (IDSEL) signal is used as a chip select signal during board configuration read and write cycles. The -Device Select (-DEVSEL) line is both an input and an output. As an input, -DEVSEL indicates if a device has assumed control of the current bus transfer. As an output, -DEVSEL shows that a device has identified itself as the target for the current bus transfer.

There are four interrupt lines (-INTA to -INTD). When the full 64 bit data mode is being used, an expansion device will initiate a -64 Bit Bus Request (-REQ 64) and await a -64 Bit Bus Acknowledge (-ACK64) signal from the bus controller. The -Bus Lock (-LOCK) signal is an interface control used to ensure use of the bus by a selected expansion device. Error reporting is performed by -Primary Error (-PERR) and -Secondary Error (-SERR) lines. Cache memory and JTAG support are also provided on the PCI bus.

In most cases, you will not be troubleshooting a bus - after all, the bus is little more than a passive connector. However, the major signals that exist on an PCI bus can provide you with important clues about the system's operation. The most effective bus troubleshooting tool available to you is a POST board (such as the ones discussed in Chapter 19). Many POST boards are equipped with a number of LEDs that display power status, along with important timing and control signals. If one or more of those LEDs is missing, a fault has likely occurred somewhere on the motherboard. Keep in mind that the vast majority of POST boards are designed for the ISA bus. You can plug a POST board (with a built-in logic probe capable of 33MHz operation) into an ISA connector, then use the logic probe to test key signals. Since the signals on a PCI bus are quite different than those on an ISA bus, try the following signals:

• Voltage - use your multimeter and check each voltage level on the PCI bus. You should be able to find -12Vdc and +5Vdc regardless of whether the bus is standard or low-voltage. For a low-voltage bus, you should also be able to find a +3.3Vdc supply. If any of these supply levels are low or absent, troubleshoot or replace the power supply.
• CLOCK (pin B16) - the Clock signal provides timing signals for the expansion device. It can be adjusted between DC (0Hz) and 33MHz. If this signal is absent, the expansion board will probably not run. Check the clock generating circuitry on the motherboard, or replace the motherboard outright.
• RST (pin B18) - the Reset line can be used to re-initialize the PCI expansion device. This line should not be active for more than a few moments after power is applied, or after a warm reset is initiated.

NOTE: PCI busses are highly dependent on a myriad of settings in the CMOS Setup. Always check for proper CMOS configuration whenever you encounter trouble with PCI devices or bus performance.

Another point to consider is that bus connectors are mechanical devices - as a result, they do not last forever. If you or your customer are in the habit of removing and inserting boards frequently, it is likely that the metal "fingers" providing contact will wear and result in unreliable connections. Similarly, inserting a board improperly (or with excessive force) can break the connector. In extreme cases, even the motherboard can be damaged. The first rule of board replacement is; always try removing and re-inserting the suspect board. It is not uncommon for oxides to develop on board and slot contacts that may eventually degrade signal quality. By removing the board and re-inserting it, you can wipe off any oxides or dust and possible improve the connections.

The second rule of board replacement is; always try a board in another expansion slot before replacing it. This way, a faulty bus slot can be ruled out before suffering the expense of a new board. Keep in mind that many current PCI motherboards have only one or two PCI slots - the remainder are ISA slots. If a bus slot proves defective, there is little that a technician can do except:

1. block the slot and inform the customer that it is damaged and should not be used.
1. replace the damaged bus slot connector (a tedious and time-consuming task) and pass the labor expense on to the customer.
1. replace the motherboard outright (also a rather expensive option).

That’s it for Chapter 39. Be sure to review the glossary and chapter questions on the accompanying CD. If you have access to the Internet, take a look at some of the various PCI resources listed below:

PCI Special Interest Group Home Page: http://www.pcisig.com/

PC2 Consulting: http://www.pc2.com/

CompactPCI Home Page: http://www.compactpci.com/

Small PCI: http://www.pcisig.com/current/smallpci/