ISA/EISA bus operations

When it was first introduced, the IBM PC was no gem. It was a slow, clunky contraption with virtually no system resources (memory, interrupts, DMA channels, and so on). Yet, the IBM PC ushered in the personal computer era that we know today. Certainly, it was not speed or efficiency that brought IBM systems to the forefront of technology. Instead, it was a revolutionary (and rather risky) concept called open architecture. Rather than designing a computer and being the sole developer of proprietary add-on devices (as so many other computer manufacturers were at the time), IBM chose to incorporate only the essential processing elements on the motherboard, and leave many of the other functions to expansion boards that could be plugged into "standard" bus connectors.

By publishing the specifications of this "standard" expansion bus and making it available to the industry as a whole, any company was then able to develop IBM-compatible adapters and add-ons. Those adapters would also work on "clone" PCs which used the same expansion bus. As a result, the PC became a processing platform for some of the most creative video, drive, and communication devices ever devised. As you might suspect, the key to an open architecture is the bus connector itself. By understanding the location and purpose of each bus signal, you can follow the operations and limitations of the bus. This chapter is intended to provide you with background information on the two classical bus architectures used in modern PCs - ISA and EISA.

The venerable Industry Standard Architecture (ISA) shown in Fig. 23-1 is the first open system bus architecture used for personal computers - any manufacturer was welcome to use the architecture for a small licensing fee. Since there were no restrictions placed on the use of ISA busses (also referred to simply as "PC busses"), they were duplicated in every IBM-compatible clone that followed. Not only did the use of a standard bus pave the way for thousands of manufacturers to produce compatible PCs and expansion devices, but it also allowed the use of standardized operating systems and applications software. Both an 8 bit and 16 bit version of the ISA bus are available, although all motherboards manufactured since the mid-1980s have abandoned the 8 bit XT version in favor of the faster, more flexible 16 bit AT version.

Use of the 8 bit XT bus started in 1982. The 8 bit ISA bus consists of a single card edge connector with 62 contacts. The bus provides eight data lines and twenty address lines which allow the board to reside within the XT's 1MB of conventional memory. The bus also supports connections for six interrupts (IRQ2-IRQ7) and three DMA channels. The XT bus runs at the system speed of 4.77MHz. Although the bus itself is relatively simple, IBM failed to publish specific timing relationships for data, address, and control signals. This ambiguity left early manufacturers to find the proper timing relationships by trial and error.

Although each connector on the bus is supposed to work the same way, early PCs designed with eight expansion slots required any card inserted in the eighth slot (the slot closest to the power supply) to provide a special "card selected" signal on pin B8. Timing requirements for the eighth slot are also tighter. Contrary to popular belief, the eighth slot has nothing to do with the IBM expansion chassis. The demands of slot 8 were to support a keyboard/timer adapter board for IBM's special configuration called the 3270PC. Most XT clones did not adhere to this "eighth slot" peculiarity.

Table 23-1 shows the pinout for an XT bus configuration. The Oscillator pin provides the 14.3MHz system oscillator signal to the expansion bus, while the Clock pin supplies the 4.77MHz system clock signal. When the PC needs to be reset, the RESET DRV pin drives the whole system into a reset state. The twenty address pins (0 to 19) connect an expansion board to the system's address bus, when address signals are valid, the Address Latch Enable (ALE) signal indicates that the address may now be decoded. The eight data lines (0 to 7) connect the board to the system's data bus.

The - I/O Channel Check (-IOCHCK) line flags the motherboard when errors occur on the expansion board. Note that the minus sign (-) preceding the signal indicates that the signal uses active-low logic. The I/O Channel Ready is active when an addressed expansion board is ready. If this pin is logic 0, the CPU will extend the bus cycle by inserting wait states. The six hardware interrupts (IRQ2 to IRQ7) are used by the expansion board to demand the CPU's attention. Interrupts 0 and 1 are not available to the bus since they handle the highest priorities of the timer chip and keyboard. The - I/O Read (-I/O R) and - I/O Write (-I/O W) lines indicate that the CPU or DMA controller want to transfer data to or from the data bus. The - Memory Read (-MEMR) and - Memory Write (-MEMW) signals tells the expansion board that the CPU or DMA controller is going to read or write data to main memory.

The XT bus supplies three DMA Requests (DRQ1 to DRQ3) so that an expansion board can transfer data to or from memory. DMA requests must be held until the corresponding - DMA Acknowledge (-DACK1 to -DACK3) signals become true. If the Address Enable (AEN) signal is true, the DMA controller is controlling the bus for a data transfer. Finally, the Terminal Count (T/C) signal provides a pulse when the DMA transfer is completed.

The limitations of the 8 bit ISA bus were soon obvious. With a floppy drive and hard drive taking up two of the six available interrupts, COM 3 and COM 4 taking up another two interrupts (IRQ 3 and IRQ 4), and an LPT port taking up IRQ 7, competition for the remaining interrupt was fierce. Of the three DMA channels available, the floppy and hard drives take two, so only one DMA channel remains available. Only 1MB of address space is addressable, and 8 data bits form a serious bottleneck for data transfers. It would have been a simple matter to start from scratch and design an entirely new bus, but that would have obsoleted the entire installed base of XT owners.

The next logical step in bus evolution came in 1984/85 with the introduction of the 80286 in IBM's PC/AT. System resources were added to the bus while still allowing XT boards to function in the expanded bus. The result became what we know today as the 16 bit AT bus. Instead of a different bus connector, the original 62 pin connector was left intact, and an extra 36 pin connector was added as shown in Table 23-2 designated "C" and "D". An extra eight data bits are added to bring the total data bus to 16 bits. Five interrupts and four DMA channels are included. Four more address lines are also provided, in addition to several more control signals. Clock speed is increased on the AT bus to 8.33MHz. It is important to note that although XT boards should theoretically work with an AT bus, not all older XT expansion boards will work on the AT bus.

The - System Bus High Enable (-SBHE) is active when the upper eight data bits are being used. If the upper eight bits are not being used (i.e. an XT board in the AT slot), -SBHE will be inactive. If the expansion board requires 16 bit access to memory locations, it must return an active -MEM CS16 signal. If the expansion board requires 16 bit access to an I/O location, it must make the -I/O CS16 signal active. The - Memory Read (-MEMR) and - Memory Write (-MEMW) signals provided by an expansion board tell the CPU or DMA controller that memory access is needed up to 16MB. The -SMEMR and -SMEMW signals only indicate memory access for the first 1MB. The -MASTER signal can be used by expansion boards that are able to take control of the bus through use of a DMA channel. It is interesting to note that small, highly-integrated AT systems are available for embedded systems and dedicated applications.

ISA 16-bit architecture that was developed on the foundation of IBM's original 8-bit XT bus. By extending the original XT bus rather than redesigning an expansion bus from scratch, IBM was able to develop their AT which would accommodate new, more sophisticated 16-bit expansion boards while still being backward compatible with the installed base of 8-bit boards. For the most part, this strategy worked quite well - the ISA bus remains a prominent feature of today's PCs. However, there is a potential problem with the ISA bus when inserting an 8-bit and 16-bit adapter that both use ROM residing in the same memory region. Such a problem generally results in trouble with the 8-bit board.

To understand where this problem arises from, you should be familiar with the ISA bus pinout as shown in Table 23-2. There is an initial 62 pin connector (A1 through A31 and B1 through B31), followed by the extended 36 pin connector (C1 through C18 and D1 through D18). Notice that Address Bits 17, 18, and 19 are repeated on pins C8, C7, and C6. When a 16 bit board is inserted in the system, those repeated address lines indicate that a memory access is about to occur somewhere within 128KB of the address signals on A17, A18, and A19 (the lower 17 address lines - A0 to A16 - specify exactly where in that 128KB range the access will take place). If an 16-bit expansion board has memory (such as a Video BIOS ROM or hard drive controller ROM) within the 128KB range about to be accessed, it responds to the system using the -MEM CS16 or -I/O CS16 lines that its memory is ready for access in 16-bit transfers. If the system receives no response from either of these lines, data is transferred in 8-bit sections.

The problem here is that 8-bit boards may also have memory within that 128KB range, but since they can not detect the three extra address lines, the board can not respond to the system. If a 16 bit board tells the system to proceed with a 16-bit data transfer, but there is also an 8-bit board in that same address range, the 8-bit board will be forced to receive 16-bit data transfers. As you might expect, this is quite impossible for an 8-bit board, so the 8-bit board will appear to malfunction. Since most expansion boards reserve their ROM addresses for the 128KB block between 768KB to 896KB (C0000h to DBFFFh, sometimes called the ROM Reserve), this is where most problems reside.

It is important for you to understand that this problem does not refer to a hardware conflict. The ROM locations of the 8-bit and 16-bit boards can certainly not overlap at any point. As you might realize, however, it is possible to have several different ROMs contained within the same 128KB of system memory. If one such ROM is on a 16-bit board and one is on an 8-bit board, the 8-bit board will likely malfunction due to the way in which 16-bit boards handle ISA bus operation. Correcting such a problem is generally a matter of replacing the 8-bit board with a 16-bit version. It might also be possible to disable the 8-bit ROM using an on-board jumper, then use the motherboard BIOS ROM instead.

The Extended ISA (or EISA) bus (Fig. 23-2) is a 32 bit bus developed in 1988/89 to address the continuing need for greater speed and performance from expansion peripherals caused by the use of 80386 and 80486 CPUs. It also did not make sense to leave the entire 32 bit bus market to IBM's MCA bus. Even though the bus works at 8.33MHz, the 32 bit data path doubles data throughput between motherboard and expansion board. Unlike the MCA bus, however, EISA ensures backward compatibility with existing ISA peripherals and PC software. The EISA bus is designed to be fully compatible with ISA boards as shown in the pinout of Table 23-3. The EISA bus switches automatically between 16 bit ISA and 32 bit EISA operation using a second row of card edge connectors and the -EX32 and -EX16 lines. Thus, EISA boards have access to all of the signals available to ISA boards, as well as the second row of EISA signals.

As with the MCA bus, EISA supports arbitration for bus mastering and automatic board configuration which simplifies the installation of new boards. The EISA bus can access fifteen interrupt levels and seven DMA channels. To maintain backward compatibility with ISA expansion boards, however, there is no direct bus support for video or audio as there is with the MCA bus. Since the EISA bus clock runs at the same 8.33MHz rate as ISA, the potential data throughput of an EISA board is roughly twice that of ISA boards. EISA systems are used as network servers, workstations, and high-end PCs of the late 1980s/early 1990s. Although EISA systems have proliferated farther than MCA systems, EISA remains a high-end standard for systems such as network servers - never really filtering down to low-cost consumer systems.

The EISA bus uses 30 address lines (Addr. 2 to Addr. 31). The lower two address lines (A0 and A1) are decoded by the Byte Enable lines (-BE0 to -BE3). Data bits 0 to 15 are taken from the ISA portion of the bus, but the upper 16 data lines are provided by (Data 16 to Data 31). The Memory/ - I/O (M/ -I/O) signal determines whether a memory or I/O bus cycle is being performed, while the Write/ - Read (W/ -R) line defines whether the access is for reading or writing. When an EISA device is allowed to complete a bus cycle, the EISA Ready (EXRDY) line is used to insert wait states. When the motherboard is providing exclusive access to an EISA board, the - Locked Cycle (-LOCK) signal is true. If an EISA board can run in 32 bit mode, the - EISA 32 bit Device (-EX32) signal is true, but if the board can only run in 16 bit mode, the - EISA 16 bit Device (-EX16) signal is true.

The - Master Burst (-MSBURST) signal is activated by the EISA bus master which informs the EISA bus controller that a burst transfer cycle will commence - thus doubling the bus transfer rate. When an external device must send a data burst, it activates the - Slave Burst (-SLBURST) line. An external device requests control of the EISA bus using the - Master Request (-MREQ) line. If the bus arbitrator decides that the requester can control the bus, a - Master Acknowledge (-MACK) signal is sent to the requesting device. A - Command (-CMD) signal is sent to synchronize the EISA bus cycle with the system clock, while the - Start (-START) signal helps to coordinate the system clock with the beginning of an EISA bus cycle. Finally, the Bus Clock (BCLK) is provided at 8.33MHz.

There’s an added wrinkle when working with EISA systems - each EISA slot must be configured through software. Whenever adding, removing, or upgrading an EISA device, you’ll need to run an EISA Configuration Utility (or ECU) to configure each EISA slot. If you don’t have an ECU handy, you may be able to download ECU v.3 from Micro Computer Systems at: http://www.mcsdallas.com/mcs/ecuv3.htm.

In most cases, you will not be troubleshooting a bus - after all, the bus is little more than a passive connector. However, the major signals that exist on an ISA or EISA bus can provide you with important clues about the system's operation. The most effective bus troubleshooting tool available to you is a POST board (such as the ones discussed in Chapter 19). Many POST boards are equipped with a number of LEDs that display power status, along with important timing and control signals. If one or more of those LEDs is missing, a fault has likely occurred somewhere on the motherboard. Refer to Chapter 19 for detailed POST board instructions.

Another point to consider is that bus connectors are mechanical devices - as a result, they do not last forever. If you or your customer are in the habit of removing and inserting boards frequently, it is likely that the metal "fingers" providing contact will wear and result in unreliable connections. Similarly, inserting a board improperly (or with excessive force) can break the connector. In extreme cases, even the motherboard can be damaged. The first rule of board replacement is; always try removing and re-inserting the suspect board. It is not uncommon for oxides to develop on board and slot contacts that may eventually degrade signal quality. By removing the board and re-inserting it, you can wipe off any oxides or dust and possible improve the connections.

The second rule of board replacement is; always try a board in another expansion slot before replacing it. This way, a faulty bus slot can be ruled out before suffering the expense of a new board. If a bus slot proves defective, there is little that a technician can do except:

1. block the slot and inform the customer that it is damaged and should not be used.
1. replace the damaged bus slot connector (a tedious and time-consuming task) and pass the labor expense on to the customer.
1. replace the motherboard outright (also a rather expensive option).

That’s it for Chapter 23. Be sure to review the glossary and chapter questions on the accompanying CD. If you have access to the Internet, take a look at some of the resources listed below:

Micro Computer Systems: http://www.mcsdallas.com/mcs/ecuv3.htm (ECU - EISA Config Util v.3.)