Equilavent gate structures

NAND & NOR deconstructed

a NAND b ~ N(a AND b)
a NOR b ~ N(a OR b)

Gates generally in terms of NAND

NOT a ~ a NAND a
a AND b ~ N(a NAND b) - taken further
a OR b ~ (Na) NAND (Nb) - taken further
a NOR b ~ (Na) AND (Nb) - taken further
a XOR b ~ (a NAND b) AND (a OR b) - taken further
a XNOR b ~ (a AND b) OR (a NOR b) - taken further

Gates generally in terms of NOR

NOT a ~ a NOR a
a AND b ~ (Na) NOR (Nb) - taken further
a NAND b ~ (Na) OR (Nb) - taken further
a OR b ~ N(a NOR b) - taken further
a XOR b ~ N(a NOR (Nb)) NOR N((Na) NOR b) - taken further
a XNOR b ~ N(a NOR b) AND N(a) NOR N(b) - taken further

Notation

Please note pre fix/polish notation is where the operator preceeds it's arguments, post fix/reverse polish is where the operator follows it's arguments and in fix is where the operator is inbetween it's arguments.

Gates in terms of NAND

AND:

In fix: (a NAND b) NAND (a NAND b)

pre fix: NAND NAND a b NAND a b

post fix: a b NAND a b NAND NAND

Equivalent logic circuit in pictorial form:

OR:

In fix: (a NAND a) NAND (b NAND b)

pre fix: NAND NAND a a NAND b b

post fix: a a NAND b b NAND NAND

Equivalent logic circuit in pictorial form:

NOR:

In fix: ((a NAND a) NAND (b NAND b)) NAND ((a NAND a) NAND (b NAND b))

pre fix: NAND NAND NAND a a NAND b b NAND NAND a a NAND b b

post fix: a a NAND b b NAND NAND a a NAND b b NAND NAND NAND

Equivalent logic circuit in pictorial form:

XOR:

In fix: ((((a NAND a) NAND b) NAND ((a NAND a) NAND b)) NAND ((a NAND (b NAND b)) NAND (a NAND (b NAND b)))) NAND ((((a NAND a) NAND b) NAND ((a NAND a) NAND b)) NAND ((a NAND (b NAND b)) NAND (a NAND (b NAND b))))

pre fix: NAND NAND NAND NAND NAND a a b NAND NAND a a b NAND NAND a NAND b b NAND a NAND b b NAND NAND NAND NAND a a b NAND NAND a a b NAND NAND a NAND b b NAND a NAND b b

post fix: a a NAND b NAND a a NAND b NAND NAND a b b NAND NAND a b b NAND NAND NAND NAND a a NAND b NAND a a NAND b NAND NAND a b b NAND NAND a b b NAND NAND NAND NAND NAND

Equivalent logic circuit in pictorial form:

XNOR:

In fix: (((a NAND b) NAND (a NAND b)) NAND (((a NAND a) NAND (b NAND b)) NAND ((a NAND a) NAND (b NAND b)))) NAND (((a NAND b) NAND (a NAND b)) NAND (((a NAND a) NAND (b NAND b)) NAND ((a NAND a) NAND (b NAND b))))

pre fix: NAND NAND NAND NAND a b NAND a b NAND NAND NAND a a NAND b b NAND NAND a a NAND b b NAND NAND NAND a b NAND a b NAND NAND NAND a b NAND a b NAND NAND a b NAND a b

post fix: a b NAND a b NAND NAND a b NAND a b NAND NAND NAND a b NAND a b NAND NAND NAND b b NAND a a NAND NAND b b NAND a a NAND NAND NAND a b NAND a b NAND NAND NAND NAND

Equivalent logic circuit in pictorial form:

Gates in terms of NOR

AND:

In fix: (a NOR a) NOR (b NOR b)

pre fix: NOR NOR a a NOR b b

post fix: a a NOR b b NOR NOR

Equivalent logic circuit in pictorial form:

NAND:

In fix: ((a NOR a) NOR (b NOR b)) NOR ((a NOR a) NOR (b NOR b))

pre fix: NOR NOR NOR a a NOR b b NOR NOR a a NOR b b

post fix: a a NOR b b NOR NOR a a NOR b b NOR NOR NOR

Equivalent logic circuit in pictorial form:

OR:

In fix: (a NOR b) NOR (a NOR b)

pre fix: NOR NOR a b NOR a b

post fix: a b NOR a b NOR NOR

Equivalent logic circuit in pictorial form:

XOR:

In fix: ((a NOR (b NOR b)) NOR (a NOR (b NOR b))) NOR (((a NOR a) NOR b) NOR ((a NOR a) NOR b))

pre fix: NOR NOR NOR a NOR b b NOR a NOR b b NOR NOR NOR a a b NOR NOR a a b

post fix: a b b NOR NOR a b b NOR NOR NOR a a NOR b NOR a a NOR b NOR NOR NOR

Equivalent logic circuit in pictorial form:

XNOR:

In fix: ((a NOR b) NOR (a NOR b)) NOR (((a NOR a) NOR (b NOR b)) NOR ((a NOR a) NOR (b NOR b)))

pre fix: NOR NOR NOR a b NOR a b NOR NOR NOR a a NOR b b NOR NOR a a NOR b b

post fix: a b NOR a b NOR NOR a a NOR b b NOR NOR a a NOR b b NOR NOR NOR NOR

Equivalent logic circuit in pictorial form: