World's first fastest full 128 bit CPU and Graphics rendering processor using embedded DRAM technology annouced by Sony Computer Entertainment Inc (SCEI)

On Tuesday the 16th of February SCEI and Toshiba made a joint annoucement at the 1999 IEEE international Solid-State Conference (ISSCC) in San Francisco about a new 128 bit microprocessor callled the Emotion EngineTM jointly researched and codeveloped by SCEI and Toshiba. Sony also took this opportunity to annouce the development of it's Graphic rendering processor using embedded DRAM technology. The purpose of the Conference was to talk about the chip's potential for future computer entertainment applications. Director Masakazu Suzuki discussed the technical specification of two chips that would work with high-end network applications with the possibility of it being the core media processor for future digital applications. The 128 bit CPU is known as the "Emotion EngineTM.

Emotion Engine


SCEI claims that in order for the Emotion Engine to process massive multimedia Information at the fastest possible speeds approaching the performance of a super computer in floating points calculations its data bus, Cache memory as well as all registers are 128 bits which are all integreted in a single chip LSI together with the state of the art 0.18 micron process technology.
It features both a CPU(Central processing Unit) and an FPU(Floating point unit) as well as 2 VPU(Vector processing units VPU1 and VPU2). The CPU will run at 300MHz with a 3.2 GB/sec bus memory bandwidth and a loating point calculating performance of 6.2 GFlops/sec. It incorporates an MPEG2 decoder circuit and high performance DMA controllers. Thus it is possible to do complicated physical calculations,NURBS curve generation and 3D geometric transformations, which are difficult to perform in real time with PC CPU's, to be performed at high speed.
Given it's massive floating point performance and it's peak calculation performance of 66 million polygons/sec in the calculation of 3D computer graphics the performance is comparable with that of high-end graphics workstations (GWS) used in motion picture production.Sony are touting the system as having data processing speed several times faster than Intel's new Pentium III technology. 
Emotion Engine Features and General Specifications



CPU core					128 bit RISC (MIPS IV-subset)
Clock Frequency					300MHz
Integer Unit					64bit (2-way Superscalar)
Multimedia extended instructions		107 instructions at 128 bit width
Integer General Purpose Register		32 at 128 bit width
TLB						48 double entries
Instruction Cache				16KB (2-way)
Data Cache					8KB (2-way)
Scratch Pad RAM					16KB (Dual port)
Main Memory					32MB (Direct RDRAM 2ch@800MHz)
Memory bandwidth				3.2GB/sec
DMA						10 channels
Co-processor1					FPU (FMAC x 1, FDIV x 1)
Co-processor2					VU0 (FMAC x 4, FDIV x 1)
Micro Memory (I:4KB D:4KB)
Vector Processing Unit				VU1 (FMAC x 5, FDIV x 2)
Micro Memory (I:16KB D:16KB)

Floating Point Performance			6.2GFLOPS
Geometry 	
+ Perspective Transformation			66Million Polygons/sec
+ Lighting					38Million Polygons/sec
+ Fog						36Million Polygons/sec
Curved Surface Generation (Bezier)		16Million Polygons/sec
Image Processing Unit				MPEG2 Macroblock Layer Decoder
Image Processing Performance			150Million Pixels/sec

Gate width					0.18 micron
VDD Voltage					1.8 V
Power Consumption				15 Watts
Metal Layers					4
Total Transistors				10.5 Million
Die Size					240 mm2
Package						540pin PBGA

REFERENCE DATA

Peak Performance approx.
Integer operation(GIPS) Main memory bandwith(GB/S) Floating point operation(GFLOPS)
Pentium II (400MHz) 1.2 0.8 0.25
Pentium III (500MHz) 1.5 1.0 2.2
Emotion Engine (300MHz) 0.5 3.2 6.2

Floating Point Vector Performance approx. (M Vector/sec)*
Geometric and perspective transfomation 1/Distance Distance Geometric Transfomation
Pentium II (400MHz) 10 18 18 16
Pentium III (500MHz) 27 27 27 38
Emotion Engine (300MHz) 67 47 67 150

Emotion Engine performance based on measured data. For Pentium II and Pentium III, theoretical maximum values based on manufacturers figures and other published data.
*4 dimensional calculation to single precision floating point.

Graphics Rendering Processor

The graphics synthesizer incorporates a massively parallel rendering engine with a 2,560 bit wide bus ( this is about 20 times the size of leading Pc-based graphics accelerators).
With the use of the embedded DRAM process technology poineered by SCEI very high pixel fill rates and drawing performance is achieved.The rendering function for 3D object is capable of generating image data that supports NTSC/PAL televisions, High Defination TV and VESA output standards. The rendering capabilities of graphic systems is defined by the memory bandwidth between the pixel engine and the Video memory. Due to the integretion of the pixel logic and the video memory on a single high performance chip. There is a 48-Gigabyte memory access bandwidth. This allows order of magnitude greater pixel fill rate performance compared to today's Pc-based graphics accelerator. This new architecture can also execute recursive multi-pass rendering processing and filter operations at a very fast speed without the assistance of the main CPU or main bus access. Graphics which have previously been possible on high-end workstations look set to be brought to the mass market through this hardware.Sony's new harware promises to model real world physics in a manner previously unseen in computer graphics.
SCEI claims the graphics synthesizer will help accelerate the convergence of movies, music and computert technology into a new form of digital entertainment.

Graphics Synthesizer - Features and General Specifications 




GS Core                                 Parallel Rendering Processor with embedded DRAM
Clock Frequency                         150 MHz
No. of Pixel Engines                    16 (in Parallel)
Embedded DRAM                           4 MB of multi-port DRAM (Synced at 150MHz)
Total Memory Bandwidth                  48 Giga Bytes per Second
Combined Internal
           Data Bus bandwidth           2560 bit
                        Read            1024 bit
                        Write           1024 bit
                        Texture         512 bit
Display Colour Depth                    32 bit (RGBA: 8 bits each)
Z Buffering                             32 bit 
Rendering Functions                     Texture Mapping, Bump Mapping
                                        Fogging, Alpha Blending
                                        Bi- and Tri-Linear Filtering
                                        MIPMAP, Anti-aliasing
                                        Multi-pass Rendering

Rendering Performance

Pixel Fill Rate                         2.4 Giga Pixel per Second
                                                (with Z buffer and Alphablend enabled)
                                        1.2 Giga Pixel per Second
                                                (with Z buffer, Alpha and Texture)
Particle Drawing Rate                   150 Million /sec
Polygon Drawing Rate                    75 Million /sec (small polygon)
                                        50 Million /sec (48 Pixel quad with Z and A)
                                        30 Million /sec (50 Pixel triangle with Z and A)
                                        25 Million /sec (48 Pixel quad with Z, A and T)
Sprite Drawing Rate                     18.75 Million (8 x 8 Pixels)

Display output                          NTSC/PAL
                                        Digital TV (DTV)
                                        VESA (maximum 1280 x 1024 pixels)
Silicon process technology              0.25 ( 4-level metal
Total number of transistors             43 Million 
Die size                                279mm2
Package Type                            384 pin BGA

Graphic Processor Reference Data approx.
Pixel fillrate(M Pixels/sec) Polygon count (M polygons/sec)
Graphic synthesizer 2400 50
InfiniteReality2 800 12
PowerVR2 200 3

CHIPS PRODUCTION INFO.
EMOTION ENGINE GRAPHICS SYNTHESIZER
Company name To be determined To be determined
Established April 1999 April 1999
Location Oita,Japan Nagasaki,Japan
Ownership 51% Toshiba, 49% SCEI 100% SCEI
Initial capital 100 million Yen to be determined
Initial production capacity 10,000 wafers a month 10,000 wafers a month
Availability Fall 1999 Spring 2000
Technology 0.18-0.15 micron process 0.18 micro embedded DRAM process

FIRST APPLICATION

The first system to use these chips is the Next Generation Playstation. It comes as no suprise since Sony had explained that the chips advanced technology will put it at the forefront of digital entertainment. With these chipsets at its heart the next-generation Playstation is able to combine richly detailed graphic quality with the ability to generate worlds,character, behaviours and complex physical simulations in real-time. The system is able to simulate not just how the images look, but how the characters and objects in a game think, act and behave. This concept is called "Emotion SynthesisTM" and requires a computer system with a massive floating-point mathematical calculation capability far beyond the current state-of-the-art workstations and approaches the performance of large scale supercomputers used in scientific simulation.
The I/O processor chip for the next generation Playstation has integreted in it USB host controller and the IEEE 1394 link and physical layers. The USB interface is compatible with OHCI (Open Host Controller Interface) and can handle transfer rates of 1.5Mbps and 12Mbps. The IEEE 1394 Can handle data transfer rates of between 100Mbps and 400Mbps. The use of these interfaces allows the connectivity of the new playstation system to a variety of other systems and comsumer products such as VCR,set top box, Digital Camera, Printer,Joystick,Keyboard and mouse amongst others.
This system is expected to be available in Japan by Spring 2000.

Back to my HomePage 1

Hosted by www.Geocities.ws