80032830:	determines tile width value, used in various ops
	accepts: A0=height
	returns V0=one of these values:
		height	value
		0x80	7
		0x40	6
		0x20	5
		0x10	4
		else	0
ADDIU	V0,R0,0020
BEQ	A0,V0,80032870	;branch if height=20
SLTIU	V0,A0,0021
BEQ	V0,R0,80032854	;branch if height>20
ADDIU	V0,R0,0010
BEQ	A0,V0,8003287C	;branch if height=10
ADDIU	V0,R0,0004	;V0=4
J	8003287C
ADDU	V0,R0,R0	;V0=0
//80032854:	height>20
ADDIU	V0,R0,0040
BEQ	A0,V0,80032878	;branch if height=40
ADDIU	V0,R0,0080
BEQ	A0,V0,8003287C	;branch if height=80
ADDIU	V0,R0,0007	;V0=7
J	8003287C
ADDU	V0,R0,R0
//80032870:	height=0x20
J	8003287C
ADDIU	V0,R0,0005	;V0=5
//80032878:
ADDIU	V0,R0,0006	;V0=6
//8003287C:
JR	RA
NOP

+-+

80032978:	set texture for DL
	accepts: A0=p->geocode,A1=image type,A2=p->image index,A3=p->palette index,SP+10=,SP+14=
ADDIU	SP,SP,FFB8
SW	S4,0030 (SP)	;S4->SP+30
ADDU	S4,A0,R0	;S4=p->geocode
SW	S0,0020 (SP)	;S0->SP+20
ADDU	S0,A1,R0	;S0=image type
SW	S5,0034 (SP)	;S5->SP+34
ADDU	S5,A2,R0	;S5=p->image index
SW	RA,0044 (SP)
SW	S8,0040 (SP)
SW	S7,003C (SP)
SW	S6,0038 (SP)
SW	S3,002C (SP)
SW	S2,0028 (SP)
SW	S1,0024 (SP)
LBU	V1,0001 (S4)	;V1=texture#
LW	A0,0058 (SP)	;A0=[SP+10 from call]
LW	S8,005C (SP)	;S8=[SP+14 from call]
SLL	V0,V1,0x1
ADDU	V0,V0,V1
SLL	V0,V0,0x2	;V0=texture#->offset
ADDU	A1,V0,S5	;A1=image index+offset
LBU	V1,0000 (A1)	;V1=image format
SB	A0,0017 (SP)	;save [SP+10 from call]
SLL	A0,A0,0x18	;A0*=0x1000000
ANDI	V0,V1,0002	;V0=image format & 2	clamps+mirrors
SLTU	V0,R0,V0	;V0=can this return anything but 0?
SUBU	V0,R0,V0	;V0=-V0
ANDI	S7,V0,0003	;S7 is either 3 or 0
ANDI	V1,V1,0004	;V1=image format & 4	clampt+mirrort
SLTU	V1,R0,V1
SUBU	V1,R0,V1	;V1=-V1
BEQ	A0,R0,80032A2C	;branch if A0=0
ANDI	S6,V1,0003	;S6 is either 3 or 0
//800329FC:
LBU	V1,0006 (A1)	;V1=1 if indexed?
ADDIU	V0,R0,0001
BEQ	V1,V0,80032A2C	;branch if flag set
ADDIU	V0,R0,0001	;V0=1
//80032A0C:
LUI	AT,8011
SB	V0,9A94 (AT)	;1->80109A94: 
LBU	V0,0001 (S4)	;V0=texture#
SLL	A0,V0,0x1
ADDU	A0,A0,V0
SLL	A0,A0,0x2	;A0=texture#->offset
JAL	800326BC
ADDU	A0,S5,A0	;A0=p->image index+offset
//80032A2C:
LBU	V1,0001 (S4)	;V1=texture#
SLL	V0,V1,0x1
ADDU	V0,V0,V1
SLL	V0,V0,0x2
ADDU	V0,V0,S5	;V0=p->image index+offset
LHU	V1,0002 (V0)	;V1=width-1
LHU	A0,0004 (V0)	;A0=height-1
LW	V0,0008 (V0)	;V0=p->image
ADDIU	S2,V1,0001	;S2=width (actual)
SW	V0,001C (SP)	;SP+1C=p->image
//80032A54:	image -> DL format thingie
SLTIU	V0,S0,0011
BEQ	V0,R0,80033474	;branch on image type 0
ADDIU	S3,A0,0001	;S3=height (actual)
SLL	V0,S0,0x2
LUI	AT,800D
ADDU	AT,AT,V0
LW	V0,2E20 (AT)	;V0=800D2E20+offset: SetImage microcode commands for each image type
JR	V0
NOP

80032A78:	image 1,2,3,4,7,8,A,C,D,E,10
LBU	V0,0001 (S4)	;V0=texture#
SLL	V1,V0,0x1
ADDU	V1,V1,V0
SLL	V1,V1,0x2
ADDU	V1,V1,S5	;V1=p->image index+offset
LBU	V0,0000 (V1)	;V0=format
ANDI	V0,V0,0001	;format&1
BEQ	V0,R0,80032CCC	;branch if bit not set
NOP
//80032A9C: format&1	ci-8bit index, 16bit color
LBU	T0,0017 (SP)	;T0=bank number?
SLL	V0,T0,0x18	;V0*=0x1000000
BEQ	V0,R0,80032C9C	;branch if zero
ADDU	A0,S3,R0	;A0=S3: height
LUI	S1,8011
LW	S1,A510 (S1)	;S1=8010A510: p->commands
ADDIU	V0,S1,0008
LUI	AT,8011
SW	V0,A510 (AT)	;save address for next command
LUI	V0,FD50
SW	V0,0000 (S1)	;save settextureimage upper word:	FD500000	ci-16bit
LW	T0,001C (SP)	;T0=p->image
ADDIU	V0,R0,FFF8
AND	V0,T0,V0	;V0=p->image, to nearest doubleword
SW	V0,0004 (S1)	;save settextureimage lower word:	address
ADDIU	V0,S1,0010
LUI	AT,8011
SW	V0,A510 (AT)	;save address for next command
LUI	V0,F550
JAL	80032830	;returns V0=line height value
SW	V0,0008 (S1)	;save rdp_settile upper word:	F5500000	ci-16bit
ADDU	A0,S2,R0	;A0=S2: width
JAL	80032830	;returns V0=line width value
ADDU	S0,V0,R0	;S0=line height value
ADDIU	A3,R0,0800	;A3=0x800
SLL	V1,S6,0x12	;V1=format&4 * 0x40000	clampt+mirrort
ANDI	S0,S0,000F
SLL	S0,S0,0xE	;S0=lineheight *0x4000	maskt
LUI	A2,0700		;A2=07000000	tile
OR	S0,S0,A2	;S0=tile | maskt
OR	V1,V1,S0	;V1=tile | clampt | mirrort | maskt
SLL	A0,S7,0x8	;A0=format&2 * 0x100	clamps+mirrors
OR	V1,V1,A0	;V1=tile | clampt | mirrort | maskt | clmaps | mirrors
ANDI	V0,V0,000F
LUI	A1,8011
LW	A1,A510 (A1)	;A1=p->current command
SLL	V0,V0,0x4	;V0=linewidth*0x10	masks
OR	V1,V1,V0	;V1=tile | clampt | mirrort | maskt | clmaps | mirrors | masks
SRL	A0,S2,0x3	;A0=S2>>3: width/8
SW	V1,000C (S1)	;save rdp_settile upper word
ADDIU	V0,A1,0008
LUI	AT,8011
SW	V0,A510 (AT)	;save p->next command
LUI	V0,E600
SW	V0,0000 (A1)	;save rdp_loadsync upper word:	E6000000
ADDIU	V0,A1,0010
LUI	AT,8011
SW	V0,A510 (AT)	;save p->next command
LUI	V0,F300
SW	R0,0004 (A1)	;save rdp_loadsync upper word:	00000000	
BEQ	A0,R0,80032B70	;branch if width<8
SW	V0,0008 (A1)	;save rdp_loadblock upper word:	F3000000	ST origin=0,0
ADDIU	A3,A0,07FF	;A3=width/8 + 0x7FF
//80032B70:
NOP
MULT	S2,S3
MFLO	V0		;V0=width*height
ADDIU	V0,V0,0001	;V0=width*height+1
SRL	V0,V0,0x1
ADDIU	V1,V0,FFFF	;V1=width*height/2, rounded up, changed to mask
SLTIU	V0,V1,0800
BEQL	V0,R0,80032B94	;if V1<0x800, set it to 0x7FF
ADDIU	V1,R0,07FF
//80032B94:
ANDI	V0,V1,0FFF
SLL	V0,V0,0xC	;V0=tile size count mask * 0x1000	lower right S
BEQ	A0,R0,80032BC8	;branch if width<8
OR	A2,V0,A2	;A2=tile | lrs
DIVU	A3,A0
BNEZ	A0,80032BB4
NOP
BREAK
//80032BB4:
MFLO	V0		;V0=widthmask/width
NOP
NOP
J	80032BCC
ANDI	V0,V0,0FFF
//80032BC8:
ANDI	V0,A3,0FFF
//80032BCC:
OR	V0,A2,V0	;V0=tile | lrs | lrt
SW	V0,000C (A1)	;save rdp_loadblock lower word:
//80032BD4:	second rdp_settile
LUI	S1,8011
LW	S1,A510 (S1)	;S1=p->cur command
ADDU	A0,S3,R0	;A0=S3: height
LUI	V1,F548		;V1=rdp_settile upper word:	ci-8bit index
ADDIU	V0,S1,0008
LUI	AT,8011
SW	V0,A510 (AT)	;save p->new command
LUI	V0,E700
SW	V0,0000 (S1)	;save upper word:	E7000000
ADDIU	V0,S1,0010
LUI	AT,8011
SW	V0,A510 (AT)	;save p->new command
ADDIU	V0,S2,0007
SRL	V0,V0,0x3	;V0=width to nearest doubleword
ANDI	V0,V0,01FF
SLL	V0,V0,0x9	;V0*=0x200	line
OR	V0,V0,V1	;V0=ci | 8bit | line
SW	R0,0004 (S1)	;save lower word:	00000000
JAL	80032830	;ret V0=line height value
SW	V0,0008 (S1)	;save rdp_settile upper word:	
ADDU	A0,S2,R0	;A0=S2: width
JAL	80032830	;ret V0=line width value
ADDU	S0,V0,R0	;S0=line height value
SLL	V1,S6,0x12	;V1=format&4*0x4000	clampt | mirrort
ANDI	S0,S0,000F
SLL	S0,S0,0xE	;S0=lineheight*0x4000	maskt
OR	V1,V1,S0	;V1=clampt | mirrort | maskt
SLL	A0,S7,0x8	;A0=format&2*0x100	clamps | mirrors
OR	V1,V1,A0	;V1=clampt | mirrort | maskt | clamps | mirrors
ANDI	V0,V0,000F
LUI	A0,8011
LW	A0,A510 (A0)	;A0=p->cur command
SLL	V0,V0,0x4	;V0=linheight*0x10	masks
OR	V1,V1,V0	;V1=clampt | mirrort | maskt | clamps | mirrors | masks
SW	V1,000C (S1)	;save rdp_settile lower word:	
//80032C60:
ADDIU	V1,S2,FFFF	;V1=widthmask
SLL	V1,V1,0x2
ANDI	V1,V1,0FFF	;V1=widthmask->10bits
SLL	V1,V1,0xC	;V1=widthmask*0x1000
ADDIU	V0,A0,0008
LUI	AT,8011
SW	V0,A510 (AT)	;save p->new command
LUI	V0,F200
SW	V0,0000 (A0)	;save rdp_settilesize upper word:	F2000000	ST origin= 0,0
ADDIU	V0,S3,FFFF	;V0=heightmask
SLL	V0,V0,0x2
ANDI	V0,V0,0FFF	;V0=heightmask->10bits
OR	V1,V1,V0	;V1=lrs | lrt
J	80032CA8
SW	V1,0004 (A0)	;save rdp_settilesize lower word
//80032C9C:
LW	V0,0000 (S8)
ADDIU	V0,V0,0007
SW	V0,0000 (S8)
//80032CA8:	format bit 1 = 0	ci-4bit index, 16bit color
LBU	V0,0001 (S4)	;V0=texture#
SLL	V1,V0,0x1
ADDU	V1,V1,V0
SLL	V1,V1,0x2
ADDU	V1,V1,S5	;V1=p->texture index + offset
LBU	V0,0000 (V1)	;V0=format
ANDI	V0,V0,0001
BNEZ	V0,80033474	;fail if format&1, which is crazy since that's how you got here in the first place...
NOP
LBU	T0,0017 (SP)
SLL	V0,T0,0x18	;V0=T0*0x1000000
BEQ	V0,R0,80032F6C	;branch if V0=0
SLTIU	V0,S7,0001	;true if no mirrors
ADDU	A1,R0,R0	;A1=0
SLTIU	V1,S6,0001	;true if no mirrort
AND	V0,V0,V1	;1 if both set
BEQ	V0,R0,80032D84	;branch if one or the other isn't...
ADDU	A2,R0,R0	;A2=0
//80032CF0:	determine if 40x40
XORI	V0,S2,0040	;V0=width^40
SLTIU	V0,V0,0001
XORI	V1,S3,0040	;V1=height^40
SLTIU	A3,V1,0001	;A3 true if height=40
AND	V0,V0,A3
BEQ	V0,R0,80032D18	;branch if image isn't 40x40
XORI	V0,S2,0020	;V0=width^20
ADDIU	A1,R0,0001	;A1=1
J	80032D84	;get on with it
ADDIU	A2,R0,0005	;A2=5
//80032D18:	determine if 20x80
SLTIU	A0,V0,0001	;A0 true if width=20
XORI	V0,S3,0080	;V0=height^80
SLTIU	V0,V0,0001
AND	V0,A0,V0
BEQ	V0,R0,80032D3C	;branch if image isn't 20x80
XORI	V0,S2,0080	;V0=width^80
ADDIU	A1,R0,0001	;A1=1
J	80032D84	;get on with it
ADDIU	A2,R0,0004	;A2=4
//80032D3C:
SLTIU	V0,V0,0001
XORI	V1,S3,0020	;V1=height^20
SLTIU	V1,V1,0001	;V1 true if height=20
AND	V0,V0,V1
BEQ	V0,R0,80032D60	;branch if image isn't 80x20
AND	V0,A0,A3
ADDIU	A1,R0,0001	;A1=1
J	80032D84	;get on with it
ADDIU	A2,R0,0003	;A2=3
//80032D60:
BEQ	V0,R0,80032D74	;branch if image isn't 20x40
AND	V0,A0,V1
ADDIU	A1,R0,0001	;A1=1
J	80032D84	;get on with it
ADDIU	A2,R0,0002	;A2=2
//80032D74:
BEQ	V0,R0,80032D84	;branch if image isn't 20x20
NOP
ADDIU	A1,R0,0001	;A1=1
ADDIU	A2,R0,0001	;A2=1
//80032D84:
LUI	S1,8011
LW	S1,A510 (S1)	;S1=p->current command
ADDIU	V0,S1,0008
LUI	AT,8011
SW	V0,A510 (AT)	;V0=p->new command
LUI	V0,FD50
SW	V0,0000 (S1)	;save rdp_settextureimage upper word:	ci | 16bit
LW	T0,001C (SP)
ADDU	V0,A1,R0
BEQ	V0,R0,80032E58
SW	T0,0004 (S1)
ADDIU	V1,R0,0800
ADDIU	V0,S1,0010
LUI	AT,8011
SW	V0,A510 (AT)
LUI	V0,E600
SW	V0,0008 (S1)
ADDIU	V0,S1,0018
LUI	AT,8011
SW	V0,A510 (AT)
LUI	V0,F300
SRL	A1,S2,0x4
SW	R0,000C (S1)
BEQ	A1,R0,80032DEC
SW	V0,0010 (S1)
ADDIU	V1,A1,07FF
NOP
MULT	S2,S3
MFLO	V0
ADDIU	V0,V0,0003
SRL	V0,V0,0x2
ADDIU	A0,V0,FFFF
SLTIU	V0,A0,0800
BNEZ	V0,80032E14
SLL	A2,A2,0x18
ADDIU	A0,R0,07FF
ANDI	V0,A0,0FFF
SLL	V0,V0,0xC
BEQ	A1,R0,80032E48
OR	A0,A2,V0
DIVU	V1,A1
BNEZ	A1,80032E34
NOP
BREAK
MFLO	V0
NOP
NOP
J	80032E4C
ANDI	V0,V0,0FFF
ANDI	V0,V1,0FFF
OR	V0,A0,V0
J	80032F58
SW	V0,0014 (S1)
ADDU	A0,S3,R0
ADDIU	V0,S1,0010
LUI	AT,8011
SW	V0,A510 (AT)
LUI	V0,F550
JAL	80032830
SW	V0,0008 (S1)	;save rdp_settile upper word:	ci | 16bit
ADDU	A0,S2,R0
JAL	80032830
ADDU	S0,V0,R0
ADDIU	A3,R0,0800
SLL	V1,S6,0x12
ANDI	S0,S0,000F
SLL	S0,S0,0xE
LUI	A2,0700
OR	S0,S0,A2
OR	V1,V1,S0
SLL	A0,S7,0x8
OR	V1,V1,A0
ANDI	V0,V0,000F
LUI	A1,8011
LW	A1,A510 (A1)
SLL	V0,V0,0x4
OR	V1,V1,V0
SRL	A0,S2,0x4
SW	V1,000C (S1)
ADDIU	V0,A1,0008
LUI	AT,8011
SW	V0,A510 (AT)
LUI	V0,E600
SW	V0,0000 (A1)	;save rdp_loadsync upper word
ADDIU	V0,A1,0010
LUI	AT,8011
SW	V0,A510 (AT)
LUI	V0,F300
SW	R0,0004 (A1)	;save rdp_loadsync lower word
BEQ	A0,R0,80032EF4
SW	V0,0008 (A1)	;save rdp_loadblock upper word:	ST origin= 0,0
ADDIU	A3,A0,07FF
NOP
MULT	S2,S3
MFLO	V0
ADDIU	V0,V0,0003
SRL	V0,V0,0x2
ADDIU	V1,V0,FFFF
SLTIU	V0,V1,0800
BEQL	V0,R0,80032F18
ADDIU	V1,R0,07FF
ANDI	V0,V1,0FFF
SLL	V0,V0,0xC
BEQ	A0,R0,80032F4C
OR	A2,V0,A2
DIVU	A3,A0
BNEZ	A0,80032F38
NOP
BREAK
MFLO	V0
NOP
NOP
J	80032F50
ANDI	V0,V0,0FFF
ANDI	V0,A3,0FFF
OR	V0,A2,V0
SW	V0,000C (A1)
LUI	S1,8011
LW	S1,A510 (S1)
ADDU	A0,S3,R0
J	800333AC
LUI	V1,F540		;V1=rdp_settile upper word: ci | 4bit index
//
SLTIU	V1,S6,0001
AND	V0,V0,V1
BEQ	V0,R0,80032FEC
ADDU	A1,R0,R0
XORI	V0,S2,0040
SLTIU	V0,V0,0001
XORI	V1,S3,0040
SLTIU	A2,V1,0001
AND	V0,V0,A2
BNEL	V0,R0,80032FEC
ADDIU	A1,R0,0001
XORI	V0,S2,0020
SLTIU	A0,V0,0001
XORI	V0,S3,0080
SLTIU	V0,V0,0001
AND	V0,A0,V0
BNEL	V0,R0,80032FEC
ADDIU	A1,R0,0001
XORI	V0,S2,0080
SLTIU	V0,V0,0001
XORI	V1,S3,0020
SLTIU	V1,V1,0001
AND	V0,V0,V1
BNEL	V0,R0,80032FEC
ADDIU	A1,R0,0001
AND	V0,A0,A2
BNEL	V0,R0,80032FEC
ADDIU	A1,R0,0001
AND	V0,A0,V1
BEQ	V0,R0,80032FF0
ADDU	V0,A1,R0
ADDIU	A1,R0,0001
ADDU	V0,A1,R0
BNEZ	V0,80033004
NOP
LW	V0,0000 (S8)
ADDIU	V0,V0,0001
SW	V0,0000 (S8)
LW	V0,0000 (S8)
J	80033470
ADDIU	V0,V0,0006

80033010:	image 5,6,9,F
LBU	V0,0001 (S4)	;V0=texture#
SLL	V1,V0,0x1
ADDU	V1,V1,V0
SLL	V1,V1,0x2
ADDU	V1,V1,S5	;V1=p->texture index+offset
LBU	V0,0000 (V1)	;V0=format
ANDI	V0,V0,0001	;V0=format&1
BEQ	V0,R0,80033264	;branch if flag=0
NOP
//80033034:	format&1	i 8bit
LBU	T0,0017 (SP)
SLL	V0,T0,0x18
BEQ	V0,R0,80033234
ADDU	A0,S3,R0
LUI	S1,8011
LW	S1,A510 (S1)
ADDIU	V0,S1,0008
LUI	AT,8011
SW	V0,A510 (AT)
LUI	V0,FD90
SW	V0,0000 (S1)	;save rdp_settextureimage upper word:	i | 16bit
LW	T0,001C (SP)
ADDIU	V0,R0,FFF8
AND	V0,T0,V0
SW	V0,0004 (S1)
ADDIU	V0,S1,0010
LUI	AT,8011
SW	V0,A510 (AT)
LUI	V0,F590
JAL	80032830
SW	V0,0008 (S1)	;save rdp_settile upper word:	i | 16bit
ADDU	A0,S2,R0
JAL	80032830
ADDU	S0,V0,R0
ADDIU	A3,R0,0800
SLL	V1,S6,0x12
ANDI	S0,S0,000F
SLL	S0,S0,0xE
LUI	A2,0700
OR	S0,S0,A2
OR	V1,V1,S0
SLL	A0,S7,0x8
OR	V1,V1,A0
ANDI	V0,V0,000F
LUI	A1,8011
LW	A1,A510 (A1)
SLL	V0,V0,0x4
OR	V1,V1,V0
SRL	A0,S2,0x3
SW	V1,000C (S1)
ADDIU	V0,A1,0008
LUI	AT,8011
SW	V0,A510 (AT)
LUI	V0,E600
SW	V0,0000 (A1)	;save rdp_loadsync upper word
ADDIU	V0,A1,0010
LUI	AT,8011
SW	V0,A510 (AT)
LUI	V0,F300
SW	R0,0004 (A1)	;save rdp_loadsync lower word
BEQ	A0,R0,80033108
SW	V0,0008 (A1)	;save rdp_loadblock upper word:	ST origin= 0,0
ADDIU	A3,A0,07FF
NOP
MULT	S2,S3
MFLO	V0
ADDIU	V0,V0,0001
SRL	V0,V0,0x1
ADDIU	V1,V0,FFFF
SLTIU	V0,V1,0800
BEQL	V0,R0,8003312C
ADDIU	V1,R0,07FF
ANDI	V0,V1,0FFF
SLL	V0,V0,0xC
BEQ	A0,R0,80033160
OR	A2,V0,A2
DIVU	A3,A0
BNEZ	A0,8003314C
NOP
BREAK
MFLO	V0
NOP
NOP
J	80033164
ANDI	V0,V0,0FFF
ANDI	V0,A3,0FFF
OR	V0,A2,V0
SW	V0,000C (A1)
LUI	S1,8011
LW	S1,A510 (S1)
ADDU	A0,S3,R0
LUI	V1,F588
ADDIU	V0,S1,0008
LUI	AT,8011
SW	V0,A510 (AT)
LUI	V0,E700
SW	V0,0000 (S1)	;save rdp_pipesync upper word
ADDIU	V0,S1,0010
LUI	AT,8011
SW	V0,A510 (AT)
ADDIU	V0,S2,0007
SRL	V0,V0,0x3
ANDI	V0,V0,01FF	;V0=width/2, rounded up
SLL	V0,V0,0x9	;V0=width/2*0x200	line
OR	V0,V0,V1
SW	R0,0004 (S1)	;save rdp_pipesync lower word
JAL	80032830
SW	V0,0008 (S1)	;save rdp_settile upper word:	i | 8bit greyscale | line
ADDU	A0,S2,R0
JAL	80032830
ADDU	S0,V0,R0
SLL	V1,S6,0x12
ANDI	S0,S0,000F
SLL	S0,S0,0xE
OR	V1,V1,S0
SLL	A0,S7,0x8
OR	V1,V1,A0
ANDI	V0,V0,000F
LUI	A0,8011
LW	A0,A510 (A0)
SLL	V0,V0,0x4
OR	V1,V1,V0
SW	V1,000C (S1)
ADDIU	V1,S2,FFFF
SLL	V1,V1,0x2
ANDI	V1,V1,0FFF
SLL	V1,V1,0xC
ADDIU	V0,A0,0008
LUI	AT,8011
SW	V0,A510 (AT)
LUI	V0,F200
SW	V0,0000 (A0)	;save rdp_settilesize upper word:	ST origin= 0,0
ADDIU	V0,S3,FFFF
SLL	V0,V0,0x2
ANDI	V0,V0,0FFF
OR	V1,V1,V0
J	80033240
SW	V1,0004 (A0)
LW	V0,0000 (S8)
ADDIU	V0,V0,0007
SW	V0,0000 (S8)
LBU	V0,0001 (S4)
SLL	V1,V0,0x1
ADDU	V1,V1,V0
SLL	V1,V1,0x2
ADDU	V1,V1,S5
LBU	V0,0000 (V1)
ANDI	V0,V0,0001
BNEZ	V0,80033474
NOP
//80033264:	format flag =0	i 4bit
LBU	T0,0017 (SP)
SLL	V0,T0,0x18	;V0=T0*0x1000000
BEQ	V0,R0,80033468	;branch if this is 0
ADDU	A0,S3,R0	;A0=height
LUI	S1,8011
LW	S1,A510 (S1)
ADDIU	V0,S1,0008
LUI	AT,8011
SW	V0,A510 (AT)
LUI	V0,FD90
SW	V0,0000 (S1)	;V0=save rdp_settextureimage upper word:	i | 16bit
LW	T0,001C (SP)
ADDIU	V0,R0,FFF8
AND	V0,T0,V0
SW	V0,0004 (S1)
ADDIU	V0,S1,0010
LUI	AT,8011
SW	V0,A510 (AT)
LUI	V0,F590
JAL	80032830
SW	V0,0008 (S1)	;save rdp_settile upper word:	i | 16bit
ADDU	A0,S2,R0
JAL	80032830
ADDU	S0,V0,R0
ADDIU	A3,R0,0800
SLL	V1,S6,0x12
ANDI	S0,S0,000F
SLL	S0,S0,0xE
LUI	A2,0700
OR	S0,S0,A2
OR	V1,V1,S0
SLL	A0,S7,0x8
OR	V1,V1,A0
ANDI	V0,V0,000F
LUI	A1,8011
LW	A1,A510 (A1)
SLL	V0,V0,0x4
OR	V1,V1,V0
SRL	A0,S2,0x4
SW	V1,000C (S1)
ADDIU	V0,A1,0008
LUI	AT,8011
SW	V0,A510 (AT)
LUI	V0,E600
SW	V0,0000 (A1)	;save rdp_loadsync upper word
ADDIU	V0,A1,0010
LUI	AT,8011
SW	V0,A510 (AT)
LUI	V0,F300
SW	R0,0004 (A1)	;save rdp_loadsync lower word
BEQ	A0,R0,80033338
SW	V0,0008 (A1)	;save rdp_loadblock upper word:	ST origin= 0,0
ADDIU	A3,A0,07FF
NOP
MULT	S2,S3
MFLO	V0
ADDIU	V0,V0,0003
SRL	V0,V0,0x2
ADDIU	V1,V0,FFFF
SLTIU	V0,V1,0800
BEQL	V0,R0,8003335C
ADDIU	V1,R0,07FF
//8003335C:
ANDI	V0,V1,0FFF
SLL	V0,V0,0xC
BEQ	A0,R0,80033390
OR	A2,V0,A2
DIVU	A3,A0
BNEZ	A0,8003337C
NOP
BREAK
//8003337C:
MFLO	V0
NOP
NOP
J	80033394
ANDI	V0,V0,0FFF
//80033390:
ANDI	V0,A3,0FFF
//80033394:
OR	V0,A2,V0
SW	V0,000C (A1)
LUI	S1,8011
LW	S1,A510 (S1)
ADDU	A0,S3,R0
LUI	V1,F580		;V1=rdp_settile:	i | 4bit color
//800333AC:	write final rdp_settile and stuff
ADDIU	V0,S1,0008
LUI	AT,8011
SW	V0,A510 (AT)
LUI	V0,E700
SW	V0,0000 (S1)
ADDIU	V0,S1,0010
LUI	AT,8011
SW	V0,A510 (AT)
SRL	V0,S2,0x1
ADDIU	V0,V0,0007
SRL	V0,V0,0x3
ANDI	V0,V0,01FF
SLL	V0,V0,0x9
OR	V0,V0,V1
SW	R0,0004 (S1)
JAL	80032830
SW	V0,0008 (S1)
ADDU	A0,S2,R0
JAL	80032830
ADDU	S0,V0,R0
SLL	V1,S6,0x12
ANDI	S0,S0,000F
SLL	S0,S0,0xE
OR	V1,V1,S0
SLL	A0,S7,0x8
OR	V1,V1,A0
ANDI	V0,V0,000F
LUI	A0,8011
LW	A0,A510 (A0)
SLL	V0,V0,0x4
OR	V1,V1,V0
SW	V1,000C (S1)
ADDIU	V1,S2,FFFF
SLL	V1,V1,0x2
ANDI	V1,V1,0FFF
SLL	V1,V1,0xC
ADDIU	V0,A0,0008
LUI	AT,8011
SW	V0,A510 (AT)
LUI	V0,F200
SW	V0,0000 (A0)	;save rdp_settilesize upper word:	ST origin= 0,0
ADDIU	V0,S3,FFFF
SLL	V0,V0,0x2
ANDI	V0,V0,0FFF
OR	V1,V1,V0
J	80033474
SW	V1,0004 (A0)
//80033468:
LW	V0,0000 (S8)
ADDIU	V0,V0,0007
//80033470:
SW	V0,0000 (S8)

80033474:	image 0,B	do nothing and return
LW	RA,0044 (SP)
LW	S8,0040 (SP)
LW	S7,003C (SP)
LW	S6,0038 (SP)
LW	S5,0034 (SP)
LW	S4,0030 (SP)
LW	S3,002C (SP)
LW	S2,0028 (SP)
LW	S1,0024 (SP)
LW	S0,0020 (SP)
JR	RA
ADDIU	SP,SP,0048
