THIRUMALA RAJU MONE

House #75, Opp. Canara Bank,

Madiwala, Bangalore 560 068.

Objective: To obtain a responsible, challenging and rewarding position where my knowledge and work experience will have valuable contribution in development of leading edge products.

Education

§ M.Tech., Industrial Electronics - Percentage - 82.16 Passed out March 2003

National Institute of Technology, Surathkal (Formerly REC Surthkal), Karnataka.

Relevant Course Work: Advanced Processor Architecture, VLSI design, Didistal speech processing, Networking and Optoelectronics

§ B.Tech., Electronics & Inst Engineering June 1997 to June 2001

JNTU-Hyd, VR Engg College, Nizamabad, AP.

Projects & Work Experience

VLSI Design

§ Designed an 8 to 256 decoder for a 16KB SRAM memory using the theory of logical effort. Involved design of 4-16 and 2-4 predecoders to meet the set area and delay constraints.

§ Designed an SRAM cell, sense amplifier, write driver and precharge driver taking into account issues like voltage swing on the bitline, wiring capacitances and diffusion capacitances of the pass transistors.

§ Designed a 1024K-bit SRAM with 64 bit words for best possible area, power and delay figures. Included using the DWL (Divided Word Line) architecture and also splitting the bitline. Also studied effects of using SRCMOS and DRMOS in the design.

§ Successfully completed the design of an 8´8 Content Addressable Memory (CAM) array using Magic. The design involved ability to write 8 bit data words to 8 separate locations and read the locations and find a matching 8 bit data word. The design included use of SIPO, PIPO shift registers and a 3:8 decoder.

§ Designed a 4-stage pipelined processor as a part of the “DIVA” project. It is a project to develop a new computing paradigm based on moving computation to data. Worked on the Design and Implementation of the Wide Word Troy 4 stage Pipeline Processor Design being used in DIVA.RTL level coding using Verilog and Floor Planning, Place & Route, Extraction/DRC/LVS Testing using Cadence, Magic and HSpice Simulations. Worked on resolving timing issues related to the design synthesis.

ASIC Design

§ Mapped software algorithms (such as bubble-sort, GCD) onto hardware/FPGAs using RTL/HDL.

§ Synthesized ASICs using Synopsys DC, and verified (board level) with Xilinx Spartan-II FPGAs.

§ Analyzed in-depth clocking/timing issues such as time-borrowing, skew tolerant circuit design, wave

pipelining, gated clocking; designed & modeled latch based pipeline architectures in VHDL.

§ Designed control and data-path units for non-linear pipelines using HDL and schematic entry tools.

§ Designed a cascaded FIFO using circular token passing mechanism.

§ Designed and simulated a single and multi-cycle CPU, 5-stage pipelined CPU (DLX Architecture)

and a 3-stage pipelined adder, using schematic entry tools.

Programmer, Mastek, Mumbai, India. August 2000 to April 2001

§ Worked on a Bangkok bank Loan Application System in Lotus Notes R5. The work involved understanding the originally developed application and then upgrading it to a newer version as well as adding new features.

§ Developed projects using Java and Oracle as a part of my training. One of the projects involved developing a site based on the popular game show “Who wants to be a millionaire”. This site was developed using applets and servlets. RMI (Remote Method Invocation) was used as the channel for client-server communication.

Computer Skills

§ Platforms: Windows 98/95/NT/Xp, MS-DOS, UNIX/Sun Solaris.

§ Languages: VHDL, Verilog, C, C++, HTML, Java, Java Servlets, ASP.

§ EDA Tools: Powerview, Magic, Irsim, HSPICE, PSPICE, Modelsim, Cadence Virtuoso, Synopsys.

References: Available upon request