Solution to problems with communication between SPARTAN3 Board and NET1 module from Digilent.

I got problems with DPIMREF interface through NET1 add-on board. I did
follow FSM constraint (FSM coding None) but it did not help: sometime EPP
bus cycle was missing write access from NET1 ethernet board to digilent main
board. I think it is because next state FSM in dpimref.vhd is driven by
asynchronous logic (astb,dstb,pwr) and that is wrong. After registering
these inputs with main clock I got reliable data communication. I have also
redesigned dpimref.vhd to remove this FSM=none logic constraint from the
file. Now can use any FSM coding I want or just let synthesis tool select
without bothering

Here you can download corrected dpimref.vhd

You will need to adapt user logic to your needs (registers) but state machine behavior should be the same.