- When pipeline is full new result is obtained every clock cycle.
- Configurable bit width through SIZE_C constant in divider entity.
- dividend allowable range of 0 to 2**SIZE_C-1
- divider allowable range of 0 to (2**SIZE_C)/2-1
- pipeline latency is 2*SIZE_C (time from latching input to result ready for sampling
View VHDL source code of divider here: dividervhd.html
Zipped divider code with automated testbench for ModelSim and two behavioral models of restoring and non-restoring dividers as VHDL procedures: divider.zip
Divider top level entity
entity divider is
generic ( SIZE_C : integer := 32 ) ; -- SIZE_C: Number of bits
port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
a : in STD_LOGIC_VECTOR(SIZE_C-1 downto 0) ;
d : in STD_LOGIC_VECTOR(SIZE_C-1 downto 0) ;
q : out STD_LOGIC_VECTOR(SIZE_C-1 downto 0) ;
r : out STD_LOGIC_VECTOR(SIZE_C-1 downto 0)
) ;
end divider ;