MICHAEL R. GALPIN
4902 Dry Oak Trail
Austin, TX 78749
(512) 899 0151
An Electrical Engineer with extensive experience in verification, programming and digital hardware design at Motorola, AMD, IBM and other Fortune 500 companies. A broad background in hardware and algorithm design and programming as well as testing, simulation, verification, and debugging problems. Expertise in 80x86 and Power PC microprocessors. Familiar with Verilog, Modelsim, Debussy, and C++.
EMPLOYMENT HISTORY
Electrical Validation /Design Engineer, Freescale, Austin, TX. 2007 to present
Run tests to characterize timing and voltage specifications, and to verify and debug SoC cores and platform IP on various Power Architecture SoC projects.
Pre-siliconValidation Engineer, Intel, Chandler, AZ. 2004 to 2005
Adapted tests, simulated, and debugged verification tests for the Tavor project. Debugged test and environment problems using the Modelsim simulator.
Updated random test geneator used to generate verilog tests for the Tavor project.
Design and Verification Engineer, ESS Technology, Austin, TX. 2000 to 2003
Adapted tests and environment, simulated, and debugged verification tests for the Jedi north bridge project. Ran logical equivalence checker to compare rtl, gates, and cadence netlists. Debugged hardware problems and wrote tests to duplicate bugs and verify fixes.
Ran logical equivalence checker and simulations to verify equivalence, timing, and design problems on the ES3898 and ES3727 DVD/VCD mpeg decoders..
Ran verification tests and debugged simulations, ran Geotest tester to screen parts for failures, debugged system boards, and put together documentation for the Mustang south bridge project.
Verification Engineer, Motorola, Austin, TX. 1997 to 2000
Developed, simulated, and debugged assembly language verification tests for the MPC 8240 embedded system based on a Power PC processor, with main responsibility simulating and debugging system design problems.
Developed, simulated, and debugged assembly language verification tests for the MPC 107 chipset using a Power PC processor, with main responsibility simulating and debugging system design problems.
Debugged and simulated assembly language verification tests, and updated a random test generator for the VeComp DSP processor, with main responsibility debugging processor design problems.
Product Development Engineer, AMD, Austin, TX. 1995 to 1997
Debugged and simulated assembly language verification tests for the K7 processor, with main responsibility debugging processor design problems.
Developed and simulated assembly language verification tests for the K5 and K6 processors, with emphasis on snoops and external processor interrupts.
Digital Design Engineer, IBM, Poughkeepsie, NY. 1988 to 1994
Chip designer and developer from high level description to gate level implementation for five chips in the Central Processor on the high performance ES/9000 computer, using tools such as synthesis, logic verification, timing, and self test, delivering chips on schedule.
Screened test floor and field problems for high performance mainframe computers. Responsible for resolving problems, implementing solutions, and managing and presenting team status. Resolved several critical customer issues that saved major accounts. Received an Excellence Team award for work on debugging field and test floor problems on the ES/9000 9021 model.
Central Processor Recovery coordinator for high performance mainframe computers. Implemented and designed new functions and algorithms as well as problem determination of test floor problems, and designed fixes involving hardware, microcode, and 31 processor controller code modules. Received an award for debugging problems on the ES/9000 9021 Processor Availability Feature.
EDUCATION
B.S., Electrical Engineering, University of Colorado, Denver, Colorado, 1988