Marcelo Hugo Martín
Engineering - Work
may 02 - feb 03
"UAR Ingeniería"
Consultant
"UAR Ingeniería"
Consultant
Design, testing and implementation of a prototype for
interfacing between proprietary equipment and internet.
Client conects to Rabbit microprocessor. RS-232, digital I/O,
TCP-IP.
oct 94 - dec 95
"Telefónica de Argentina"
Becario Rentado | Profesional Junior
"Telefónica de Argentina"
Becario Rentado | Profesional Junior
Design, testing and implementation of system
for testing telephone wires.
Programmed using Lab-View.
Clients connect to a monitor computer via internet.
Monitor computer uses IEEE-488 and ISA I/O board
to control data acquisition devices and a matrix of relays.
On leaving Telefónica, the prototype is in an advanced stage of implementation. It controls the matrix of relays, the I/O board, and the data acquisition devices. Clients connect with no known errors.
On leaving Telefónica, the prototype is in an advanced stage of implementation. It controls the matrix of relays, the I/O board, and the data acquisition devices. Clients connect with no known errors.
jun 91 - jun 92
"University of California"
Research Assistant
"University of California"
Research Assistant
Design, test and implementation of the
prototype of BORG. BORG consists of an ISA board
that holds five XIlinx re-programmable FPGAs.
It allows for the design, testing and implementation
of digital circuits inside of the computer, without
the need to build a prototype.
Works with no known errors.
Document in citeseer.nj.nec.com: BORG
Works with no known errors.
Document in citeseer.nj.nec.com: BORG
jun 92 - jun 94
"University of California"
Student | Research Assistant
"University of California"
Student | Research Assistant
Title of thesis: "A reconfigurable Hardware
Accelerator for Back-Propagation Connectionist Classifiers".
Design, implementation and test of the prototype of ACME.
The accelerator allows for the implementation of a reconfigurable network of up to fourteen neurons.
Design, implementation and test of a reconfigurable Clos-like interconnection network among the neurons, the interface to the Sparc computer, and of supporting software.
This is a joint project with another student. The design of the neurons and testing of the system with five neurons are in Aaron Ferrucci's Master Thesis: "ACME: A Field Programmable Gate-Array Implementation of a Self-Adapting and Scalable Connectionist Classifier").
At the date of submittal of the thesis there are five FPGAs connected to the Clos interconnection network. Works with no known errors.
Document in citeseer.nj.nec.com: ACME
Design, implementation and test of the prototype of ACME.
The accelerator allows for the implementation of a reconfigurable network of up to fourteen neurons.
Design, implementation and test of a reconfigurable Clos-like interconnection network among the neurons, the interface to the Sparc computer, and of supporting software.
This is a joint project with another student. The design of the neurons and testing of the system with five neurons are in Aaron Ferrucci's Master Thesis: "ACME: A Field Programmable Gate-Array Implementation of a Self-Adapting and Scalable Connectionist Classifier").
At the date of submittal of the thesis there are five FPGAs connected to the Clos interconnection network. Works with no known errors.
Document in citeseer.nj.nec.com: ACME
oct - dec 92
"University of California"
Student, two people
"University of California"
Student, two people
Simulation of the pipelined version of the DLX processor
as described in Patterson & Hennessy's book: "Computer Architecture,
a Quantitative Approach". Programmed in verilog.
Executes code generated by the dlxcc compiler.
Contribution: some of the software modules, general design, processor schematics, signals and datapath checking. Works with no known errors.
Contribution: some of the software modules, general design, processor schematics, signals and datapath checking. Works with no known errors.
abr - jun 91
"University of California"
Student, two people
"University of California"
Student, two people
Design, implementation and testing of
a digital tetris machine. Conceived as a finite-state
machine. Implemented in two Xilinx xc3020 FPGAs.
The algorithm is sub-optimal due to resource limitations.
The host computer generates the type and initial rotation
of the tile. The machine returns where the tile should be
dropped and with what rotation.
Contribution: Logic design for part of the project. General testing. Works with no known errors.
Contribution: Logic design for part of the project. General testing. Works with no known errors.
oct - dec 91
"University of California"
Student, two people
"University of California"
Student, two people
Design, implementation and testing of
microprocessor based system that detects a
coded infra-red signal emitted from a TV
remote control. The processor activates LEDs
and displays simulating the basic functions of
a TV set (on/off, channel, volume, mute). z80.
Contribution: design and implementation of hardware. General testing. Works with no known errors.
Contribution: design and implementation of hardware. General testing. Works with no known errors.
oct - dic 90
"University of California"
Student, two people
"University of California"
Student, two people
Design, implementation and testing of an 8-bit
processor (Acorn VIII) based in two AM2903A bit-slices.
Design, implementation and testing of registers, data
path, memory access, system control and ALU. Design, implementation
and testing of its assembly language.
The data-bus, the registers, the ALU, and the memory are
implemented in hardware. The instruction register and the
program control reside in an IBM XT.
Interfacing tools are used for the communication between
the emulator/monitor and the hardware.
Contribution: Hardware design and implementation. General testing. Works with no known errors.
Contribution: Hardware design and implementation. General testing. Works with no known errors.
jan - mar 92
"University of California"
Student, two people
"University of California"
Student, two people
Design, implementation, testing and entry in
competition of Mino-Mouse. This is a mechanical mouse
that solves a novice maze. Two stepper motors are
connected to a pair of plastic wheels. A board
holds the electronics for driving the motors. A second
board holds a microprocessor and an FPGA that contain
the logic to solve the maze.
Six proximity sensors detect the walls of the maze.
Mino Mouse obtained the third place in an IEEE hosted
competition. It works with no known errors according
to the specification of the problem to solve.
Contribution: design and implementation of the FPGA logic. General testing.
Contribution: design and implementation of the FPGA logic. General testing.