SUBJECT
|
Class strength
|
YEAR/SEM
|
SECTION
|
CLASS
|
LOAD
|
||
L
|
T
|
P
|
|||||
|
Computer Architecture & Organization CSE- 210 E
|
60
|
3rd
/ 5th
|
A
|
ECE
|
3
|
3
|
-
|
S.No
|
TOPIC
|
UNIT
|
Assign
ment Link
|
Ref/Text Book
|
Due Date
|
PPT/PDF/
DOC
|
Date Covered
|
Web ref
|
L1, L2,
L3 |
Basic Principles: Boolean algebra and Logic gates,
Combinational logic blocks(Adders, Multiplexers, Encoders, de-coder)
|
1
|
|
|
|
PPT1
|
|
|
L4,
L5 |
Sequential logic blocks
(Latches, Flip-Flops, Registers, Counters)
|
1
|
|
|
|
PPT2
|
|
|
L6
|
General System
Architecture:
Store program control concept,
|
2
|
|
R1-Computer System Architecture by M.Mano
|
|
PPT3
|
|
|
L7
L8 |
Flynn’s classification
of computers (SISD, MISD, MIMD);
|
2
|
|
|
|
PPT4
|
|
|
L9
|
Multilevel viewpoint of a
machine: digital logic, micro architecture, ISA, operating systems, high
level language
|
2
|
|
|
|
PPT5
|
|
|
L10,
L11
|
Structured
organization; CPU, caches, main memory, secondary memory units & I/O;
Performance metrics; MIPS, MFLOPS. |
2
|
|
|
|
PPT6
|
|
|
L12
|
Instruction Set Architecture: Instruction set based classification
of processors (RISC, CISC, and their comparison); |
3
|
|
|
|
PPT7
|
|
|
L13,
L14 |
Addressing modes:
register, immediate, direct, indirect, indexed;
|
3
|
|
|
|
PPT8
|
|
|
L15
L16 |
Operations
in the instruction set; Arithmetic and Logical, Data Transfer, Control Flow; |
3
|
|
|
|
PPT9
|
|
|
L17
|
Instruction
set formats (fixed, variable, hybrid); |
3
|
|
|
|
PPT10
|
|
|
L18
|
Language
of the machine: 8086: simulation using MSAM. |
3
|
|
|
|
PPT11
|
|
|
L19
L20 |
Basic non pipelined
CPU Architecture:
CPU Architecture types (accumulator, register, stack, memory/ register)
|
4
|
|
|
|
PPT12
|
|
|
L21
|
Detailed data path of a
typical register based CPU
|
4
|
|
|
|
|
|
|
L22
|
Fetch-Decode-Execute
cycle (typically
|
4
|
|
|
|
|
|
|
L23
|
Microinstruction
sequencing, implementation of control unit,
|
4
|
|
|
|
|
|
|
L24
|
Enhancing performance
with pipelining.
|
4
|
|
|
|
|
|
|
L25,
L26
|
Memory Hierarchy
& I/O Techniques: The need for a memory hierarchy (Locality of reference principle, Memory
hierarchy in practice: Cache, main memory and secondary memory, Memory
parameters: access/ cycle time, cost per bit);
|
5
|
|
|
|
|
|
|
L27,
L28
|
|
5
|
|
|
|
|
|
|
L29
L30 |
Cache memory
(Associative & direct mapped cache organizations.
|
5
|
|
|
|
|
|
|
L31,
L32
|
Introduction to
Parallelism:
Goals of parallelism (Exploitation of concurrency, throughput enhancement);
|
6
|
|
|
|
|
|
|
L33
L34 |
Amdahl s law;
Instruction level parallelism (pipelining, super scaling basic features);
|
6
|
|
|
|
|
|
|
L35
|
Processor level
parallelism (Multiprocessor systems overview).
|
6
|
|
|
|
|
|
|
L36,
L37
|
Computer Organization
[80x86]: Instruction
codes, computer register, computer instructions, timing and control,
|
7
|
|
|
|
|
|
|
L38,
L39
|
Instruction
cycle, type of instructions, memory reference, register reference. I/O
reference |
7
|
|
|
|
|
|
|
L40,
L41
|
Basics
of Logic Design, accumulator logic, Control memory, address sequencing, microinstruction
formats, micro-program sequencer, |
7
|
|
|
|
|
|
|
L42,
L43
|
Stack
Organization, Instruction Formats, Types of interrupts; Memory Hierarchy.
|
7
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Text Books:
T1- Computer Organization and Design, 2nd Ed., by David
A. Patterson and John L. Hennessy, Morgan 1997, Kauffmann.
T2-
Computer Architecture and Organization, 3rd
Edi, by John P. Hayes, 1998, TMH.
Reference Books:
R1-Operating Systems Internals and Design Principles by William Stallings,4th edition, 2001, Prentice-Hall Upper Saddle River, New Jersey
R2- Computer Organization, 5th Edi, by Carl Hamacher, Zvonko Vranesic,2002, Safwat
Zaky.
R3- Structured Computer Organisation by
A.S. Tanenbaum, 4th
edition, Prentice-Hall of
R4- Computer Organisation &
Architecture: Designing for performance by
R5- Computer System Architecture by M. Mano, 2001,
Prentice-Hall.
R6- Computer Architecture- Nicholas Carter, 2002,
T.M.H.