\ Discrete Event Simulation -------------------------------------------------
DECIMAL 100 CONSTANT maxregs                 \ # of regs allowed in model
CREATE currnt  maxregs CELLS ALLOT           \ current state of registers
CREATE pending maxregs CELLS ALLOT           \ state after the next clock
VARIABLE REGISTERS   0 REGISTERS !           \ registers in the list
: undef  -1 abort" Undefined I/O signal detected" ;
currnt maxregs CELLS -1 fill pending maxregs CELLS -1 fill
: process ; : clkmem ;                       \ processes to build on
: clkregs    ( -- ) pending currnt registers @ MOVE ; \ clock registers
: w:  ( <name> -- ) CREATE -1 , DOES> ;      \ wire

: r:  ( <name> -- ) registers @ currnt + CONSTANT     \ register
     1 CELLS registers +!  registers @ maxregs CELLS = IF ABORT THEN ;
: !!   ( val n -- ) [ pending currnt - ] LITERAL + ! ;  \ pending value

: ~   ( <name> -- ) ' , ;                    \ add to table
: $   ( <name> -- ) VARIABLE ;               \ for enumerated types
: in: ( xt <name> -- ) >IN @ >R DEFER R> >IN ! \ an input signal
     ( exec: -- n ) POSTPONE IS ;            \ xt is an action for the signal
: ev: ( <name> -- ) >IN @ >R DEFER R> >IN !  \ an undefined event
     ( exec: n -- ) ['] DROP  POSTPONE IS ;




