The Forth hardware simulator can simulate common defects in ASICs to check testbenches for fault coverage. 

NOFAULT  ( -- )                Clears the fault list (default).
FAULT    ( mask xt <name> -- ) Creates a fault. <name> is a wire or register.
STUCK_0	 ( -- xt )             Stuck at '0' fault.	       
STUCK_1	 ( -- xt )             Stuck at '1' fault.	       
SLOW	 ( -- xt )             Delayed past clock fault.	       
SLOW_RISE( -- xt )             Slow 0>1 transition fault.	       
SLOW_FALL( -- xt )             Slow 1>0 transition fault.	       

The CD16 simulator supplies some words for batch testing:

GOLDSIM  ( steps -- )          Marks the results of a good simulation.
MUSTFAIL ( -- )                Runs the testbench one time expecting failure.

The following code runs several simulations with stuck bits.

NOFAULT 5000 GOLDSIM                       \ 5000 steps with known good hardware
NOFAULT 1   STUCK_0 FAULT W      MUSTFAIL  \ bit 0 of W is stuck low
NOFAULT 4   STUCK_1 FAULT W      MUSTFAIL  \ bit 2 of W is stuck high
NOFAULT 5 SLOW_FALL FAULT SP     MUSTFAIL  \ bits 2 and 0 of SP are slow to fall
NOFAULT 1      SLOW FAULT OV     MUSTFAIL  \ overflow bit is delayed
NOFAULT 1 SLOW_RISE FAULT predec MUSTFAIL  \ predec line is slow to rise
.( Congratulations!)
