Quick Start:

A synthesizable model is ready to simulate using a testbench. Load order is:
        CD16PKG.VHD     \ package
        STKRAM.VHD
        DMEM.VHD        \ data RAM model
        PMEM.VHD        \ ROM model with test suite
        CD16.VHD        \ CPU
        COP16.VHD       \ coprocessor
        TESTSOC.VHD     \ CD16, memory, I/O and timer interrupt
        BENCH.VHD       \ top level

During the simulation, some undefined signals will propagate through adders but
won't be stored anywhere. You should turn off these kinds of warnings since the
testbench will detect invalid results. Also, set the VHDS simulator to break on 
Error.

The compiler and software simulator run using Win32forth, which is available 
free on the Internet. From the Win32forth console, load R.F using the File Load 
menu. R.F is in the 4th folder.

Type FLOAD SUITE.F to load the assembly test. Or, use the file menu. This will 
save a file ROM.HEX for use by the simulator. It also saves a disassembled 
version in ROM.TXT. You could load CD16.F instead, which creates code to run 
several benchmarks. Type BYE to quit Win32forth.

Launch Win32forth again, but this time load SIM.F. You can single-step through
ROM.HEX by typing WIN. Or, you can generate a synthesizable ROM by typing
SYNSAVE PMEM.VHD. A VHDL file will automatically be generated.

You can generate a stimulus file for use in the testbench (BENCH.VHD) by typing
the number of steps followed by STIMULUS and a file name.
Example: 1000 STIMULUS STIM.TXT. The simulator clocks the CPU model to create
test vectors that are expressed using ASSERT statements. Open this file, then
cut and paste it into the testbench file BENCH.VHD.

To generate a ROM for Xilinx Spartan2, use the number of cells folowed by S2ROM
and a filename. Example: 0x400 S2ROM MyROM.VHD creates a 1Kx16 program ROM 
out of 256x16 RAM blocks. Use V2ROM to generate a ROM using 1Kx18 blocks found 
in Virtex2 and Spartan3.

The Xilinx folder contains memories suitable for synthesizing with XST. The 
post-synthesis VHDL model works with the testbench. The files you need to 
demonstrate this are:

	BENCH.VHD
	testsoc_translate.vhd

Note that the latter is generated by XST. One of XST's implementation buttons 
does it.

