; TITLE 4-bit 2's Complimentor ; CHIP 2COMP NFX780_84 ; Is this the right chip ??? ; INPUTS PIN [47:50] a[0:3] ; the 4 bit number to be 2's complemented ; OUTPUTS ; +---s6---+ PIN 34 s0 ; | | PIN 35 s1 ; s5 s4 PIN 36 s2 ; | | PIN 37 s3 ; +---s3---+ PIN 39 s4 ; | | PIN 40 s5 ; s2 s1 PIN 41 s6 ; | | ; +---s0---+ PIN cp[0:3] ; the 2's complement of a[0:3] PIN cout ; dump the carry output here PIN inv[0:3] ; the inversion of a[0:3] will be stored on these nodes ; UNUSED PINS PIN [51] unused0 PIN [77:78] unused[1:2] EQUATIONS inv[0:3]=/a[0:3] ; inverts all 4 inputs ; Perform the 2's complement: invert the input and add 1 MODULE add4 FILE 4bfuladd ( a[0:3]=inv[0:3], b0=VCC, b1=GND, b2=GND, b3=GND, cin=GND, sum[0:3]=cp[0:3], cout=cout ) ; Decode the 2's complement and output it to the 7-segment display T_TAB ( cp3 cp2 cp1 cp0 >> s0 s1 s2 s3 s4 s5 s6 ) 0 0 0 0 : 1 1 1 0 1 1 1 ; 0 0 0 0 1 : 0 1 0 0 1 0 0 ; 1 0 0 1 0 : 1 0 1 1 1 0 1 ; 2 0 0 1 1 : 1 1 0 1 1 0 1 ; 3 0 1 0 0 : 0 1 0 1 1 1 0 ; 4 0 1 0 1 : 1 1 0 1 0 1 1 ; 5 0 1 1 0 : 1 1 1 1 0 1 1 ; 6 0 1 1 1 : 0 1 0 0 1 0 1 ; 7 1 0 0 0 : 1 1 1 1 1 1 1 ; 8 1 0 0 1 : 1 1 0 1 1 1 1 ; 9 1 0 1 0 : 0 1 1 1 1 1 1 ; A 1 0 1 1 : 1 1 1 1 0 1 0 ; b 1 1 0 0 : 1 0 1 0 0 1 1 ; C 1 1 0 1 : 1 1 1 1 1 0 0 ; d 1 1 1 0 : 1 0 1 1 0 1 1 ; E 1 1 1 1 : 0 0 1 1 0 1 1 ; F ; SIMULATION: Run through all 16 possible inputs and spit out it's 2's complement ; expected output: Should effectively count down from F - 0 SIMULATION VECTOR in_a := [ a3, a2, a1, a0 ] VECTOR comp := [ cp3, cp2, cp1, cp0 ] VECTOR seg_display := [s0, s1, s2, s3, s4, s5, s6] TRACE_ON in_a comp seg_display FOR i:=0 TO 15 DO BEGIN SETF in_a := i END