71 Birch Island Road
Webster, Ma. 01570
h(508) 949-6893 or [email protected]
PERSONAL:
Single U.S. Citizen D.O.B. 4/10/58 6'0" 175 lbs.
EDUCATION:
1983 B.S. Electrical Engineering @ Southern Illinois University, Carbondale, Illinois.
1978 A.S. Electrical Technology @ Dutchess Community College, Poughkeepsie, New York.
OBJECTIVE:
Seeking a position in ASIC Design with project Architecture/Design responsibilities. Flexible on area of assigned work but most interested in computer Graphics/Video designs. The whole range of multimedia products from 3D pipeline to rendering into unique FrameBuffer organizations are of interest. My belief to make leadership products is through cleaver and inventive ASIC implementation. I enjoy hands-on practical work and people involvement.
BUSINESS EXPERIENCE:
2/00 - present Independent contracting at ATI Research:
Worked as an independent Contractor at ATI. I did the Architecture and Design of a Compressed Fragment based multisampling up to 8 samples per pixel. This was used in PC Gaming and later adopted for X-Box. I have several Patents pending on this. I also have some patents on Color and fragment cache processing.
9/99 - 1/00 Intrinsix contracting at Analog Devices: Principal Consulting Engineer
Lead a group of 5 people at Analog Devices to model a DSP with UTOPIA in a large FPGA.
2/98 - 8/99 Intrinsix contracting at 3Com: Principal Consulting Engineer
Lead a group of 8 people at 3Com to bring a 10/100 Either Net NIC ASIC with full data encryption/decryption to tape out and production. This was about 1.5Million Gate design fully functional FIRST Pass.
4/97 - 1/98 Compaq:
Joined the ALPHA processor Architecture team. Here I developed a new set of instruction for 3D Graphics such as for assisting in texture mapping and color interpolation.
1/97 - 4/97 Digital Equipment :
Architecture and Verilog Coding for Video Editing Chip in Consumer Market:
Camcorder, NTSC/PAL, and frame time stamp input, MPEG I-Frame encoding, Real time video special effects via Alpha Blending and Chroma Keying. Graphics Overlays for text and cartoon animation merged with Video. This is all output to a video encoder chip then to a VCR.
7/96-12/96 Digital Equipment :
MultiMedia: Video/Graphics memory architectures for moving MPEG Data.
Mapping of Windows95 DDK, OpenGL, and Direct-Draw games support into Hardware.
Mapped DSP parallel algorithms for Graphics, MPEG/JPEG, & Gouraud Shading
Overlay functions to render Graphics and Video into same Display memory .
5/95-6/96 Digital Equipment :
MultiMedia Hardware Designs:
135mhz Display Refresh Chip for Video and Graphics Streams:
Removing Video aliasing artifacts due to interlace and motion
YUV Video and 8,16,24 Bit/Pixel Graphics support in a single chip
YUV and RGB data can be Alpha blended or Chroma-Keyed
YUV to RGB Color Space and Color Format Conversion
Video Blending of even and odd fields for Flicker Reduction of synthesized images
Compression/Decompression of Video and Audio Data.
CHIP DESIGN EXPERIENCE
2/94-4/95 IBM:
Architecture and High Level design of RAMDAC Similar to Bt463 window RAMDAC part
1/92-1/94 IBM:
Architecture and Lead Design of 2D Graphics Raster Processor (PAX) with Integrated Bus Interface for POWERPC Microprocessor
1/91-1/92 IBM:
Architecture and Lead Design of 2D Graphics Raster Processor for IBM PC.
Highlights of chip as follows:
Designed for PC graphics 60K Gates Standard Cell Design (LSI), 28MHz
Similar set of function as above
Edge Trigger Scan design
1/89-1/91 IBM:
Single Designer of 2D Graphics Raster Processor
Highlights of chip as follows:
Designed for PC graphics
35K Gates, Gate Array Design (LSI), 28MHz
Similar set of function as above
Also Designed the graphics Card and worked with technicians
6/86-12/88 IBM:
Design of Voice Recognition�s chip
Highlights of chip as follows:
4k Gates, Gate Array
Voice input from microphone to DSP
Voice out to Speakers
9/83-12/88 IBM:
Design of DMA Controller chip
9/78-8/80 IBM:
Worked as a electronics technician
Designed and built boards for multi processor models
Wired test cards
Built power supply's
AWARDS & QUOTES
Outstanding Technical Achievement Award for Leadership on PowerPC 2D Graphics Pixel Accelerator for X (PAX) Design.
Received invention achievement awards for several US patents (5315540,5305431)
Quote based on my design,:. �PC MAGAZINE�,:. May 31,1994
"IBM's PowerPC turned in the highest graphics score"
"outperform Hewlett-Packard"
"-itself an impressive graphics machine"
Article about my design in.�Electronic Design� :.July 25, 94'
"PAX Top-Performing Graphics chip"
SKILLS & Strong Points:
I Can take your idea on a napkin to a product.
VHDL & Verilog High Level Design and simulation tools. (Synopsys)
Given several Presentation on 2D and 3D X-Window Hardware Algorithms
Held training classes for 2D Raster Processor Designs
Windows, Unix Operation System, and X-Windows
Writing HTML for Internet browsers like Netscape
MS Word, Ami Pro,
Very familiar with Windows DDK and competitive rendering designs
Interfacing with many vendors and different technologies
Designing hardware for testability
Designs won many performance awards
PUBLICATIONS and INVENTIONS:
� Title: LINE DRAWING USING A DSP ARRAY, 25+ MILLION VECTORS PER SEC.
� Title: 2D GRAPHICS USING SYSTEM MEMORY FOR FRAME BUFFERS AND NO VRAM
� Title: AN INTEGRATED SCHEME FOR DITHERING 24 BITS OF TRUE COLOR DOWN TO 4/8/12 OR 16 BITS WITH REDUCED ERROR
� Title: FRAME BUFFER DATA USED AS RAMDAC COMMANDS
� Title: INCREASED PERFORMANCE ACROSS AN I/O BUS BY USING FIFO FUNNELS
� Title: ADDRESSING EXTRA MEMORY FOR CLIPPING PLANES
� Title: A METHOD AND SYSTEM FOR RENDERING POLYGONS ON A RASTER
� Title: BINARY SIGNAL HARDWARE DIVIDER AND METHOD
� Title: HARDWARE CLIPPING AND FRAME BUFFER SELECT USING A PRIORITY SCHEME WITH WINDOW ID
� Title: FAST HARDWARE AREA FILL USING BLOCK WRITE CYCLES
� Title: INTERLEAVING THROUGH FRAME BUFFERS
� Title: METHOD AND APPARATUS FOR DRAWING ANTIALIASED LINES ON A RASTER DISPLAY
� Title: A VIDEO FRAME BUFFER WITH INCREASED PERFORMANCE CAPABILIT
� Title: EXTERNAL CONTROL OF INTERNAL STATE MAHICNE
� Title: MULTI-WAY PROGRAMMABLE BIT BLOCK TRANSFER (BIT BLT)
