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Gururaj.K.Kulkarni #27/1,Above shilpa service centre, 4th Model House Street, Near Nagasandra circle,Basavanagudi, Bangalore-04. : 98441-31152.
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Objective: Seeking a challenging position in VLSI design in a premier firm. Interested in working
on ASIC Design, FPGA Design, VLSI Design on WIN NT, SUN SOLARIS platforms..
Profile :
Has a bachelor’s degree in Electronics and communications with two years of experience in IT industry.
Areas of Expertise :
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Digital Design, Microprocessors, BUS standards·
HDL: Verilog RTL and Behavioral Modeling.·
Building Verification environment.·
Xilinx FPGAs.·
VLSI System Design·
Unix,c
Development Environment :
Hardware : SUN Solaris, Pentium
Tools : Cadence( ncverilog , Verilog-XL,HAL-lint tool,Vericover-coverage tool),
Synopsys( VCS- simulator, DC), Xilinx(DM-PnR tool), Synplicity (simplify)
Operating Systems : UNIX, WINDOWS
Languages : VERILOG, C.
Professional Experience Highlights:
1. Period : (Mar2001 – till date)
a. Areas Worked On: Bluetooth base band controller.
b. Organisation : MindTree Technologies, Bangalore.
c. Client: Embedded wireless devices ,USA.
d. Project Highlights:
1. Designed and tested the packet composer / decomposer consisting of CRC/FEC calculator, access code generator, scrambler and serializer.
2. Designed the complete test environment for Baseband controller and carried out the testing along with a team of 3 engineers.
e. Tools/Skills used:
1. verilog simulators- ncverilog , verilog-XL.
2. Synthesys tools: Ambit Build gates and simplify.
3. Place and Root tool: Xilinx’s Design Manager.
4. Code-coverage analysis tool: Vericover from cadence.
5. Lint analysis tool: HAL from cadence.
6. Scripting used: c-shell scripting and perl.
7. PLI’s .
2. Period : ( Sep2000 – Feb 2001)
a. Areas Worked On: Architectural Design of ISDN D-Channel controller.
b. Organization: MindTree Technologies, Bangalore.
c. Client: Hitachi Micro Systems Europe limited.
d. Project Highlights:
1 Designed the processor interface block for ISDN D-Channel controller.
2 Designed the complete test environment for testing ISDN D-Channel controller and carried out the testing of the same.
e. Tools/Skills used:
1. verilog simulators- verilog-XL.
2. Synthesys tools: Ambit Build gates and simplify.
3. Code-coverage analysis tool: Vericover from cadence.
4. Scripting used: c-shell scripting.
3. Period : ( Feb 2000- Sep 2000)
a. Areas worked on :Bus interface Unit.
b. Client : C-Cube Microsystems, USA.
c. Organisation: Qual core logic ltd, Hyderabad.
d. Project highlights:
1. Tested the DMA controller in the BIU.
2. Designed and tested IDE with DMA33 interface module.
3. Designed and tested a PCMCIA interface module.
f. Tools/Skills used:
1. verilog simulator- VCS, Verilog-XL.
2. Synthesys tools: Design Compiler.
3. Scripting used: c-shell scripting.
Training Programmes participated / Certifications :
Undergone Intensive training in VLSI designing and Synthesis at VEDA –IIT (VLSI Engineering & Design Automation), Hyderabad on the following subjects.
> Digital fundamentals.
> Advance digital design.
> Verilog HDL.
> FPGA Prototyping & Architecture.
> ASIC Synthesis using Design compiler (synopsys)
> AMBIT Build gates.
Educational Details:
Bachelor of Engineering (Electronics & communication)
College : SDM College of Engg.&Tech,Dharwad.
University : Karnataka University, Dharwad.
Result : 80 % (Aggregate)