#include <lpcVIC.h>
Data Fields | |
| REG32 | irqStatus |
| REG32 | fiqStatus |
| REG32 | rawIntr |
| REG32 | intSelect |
| REG32 | intEnable |
| REG32 | intEnClear |
| REG32 | softInt |
| REG32 | softIntClear |
| REG32 | protection |
| REG32 | _pad0 [3] |
| REG32 | vectAddr |
| REG32 | defVectAddr |
| REG32 | _pad1 [50] |
| union { | |
| struct { | |
| REG32 vectAddr0 | |
| REG32 vectAddr1 | |
| REG32 vectAddr2 | |
| REG32 vectAddr3 | |
| REG32 vectAddr4 | |
| REG32 vectAddr5 | |
| REG32 vectAddr6 | |
| REG32 vectAddr7 | |
| REG32 vectAddr8 | |
| REG32 vectAddr9 | |
| REG32 vectAddr10 | |
| REG32 vectAddr11 | |
| REG32 vectAddr12 | |
| REG32 vectAddr13 | |
| REG32 vectAddr14 | |
| REG32 vectAddr15 | |
| } | |
| REG32 vectAdrArray [16] | |
| }; | |
| REG32 | _pad2 [48] |
| union { | |
| struct { | |
| REG32 vectCntl0 | |
| REG32 vectCntl1 | |
| REG32 vectCntl2 | |
| REG32 vectCntl3 | |
| REG32 vectCntl4 | |
| REG32 vectCntl5 | |
| REG32 vectCntl6 | |
| REG32 vectCntl7 | |
| REG32 vectCntl8 | |
| REG32 vectCntl9 | |
| REG32 vectCntl10 | |
| REG32 vectCntl11 | |
| REG32 vectCntl12 | |
| REG32 vectCntl13 | |
| REG32 vectCntl14 | |
| REG32 vectCntl15 | |
| } | |
| REG32 vectCtlArray [16] | |
| }; | |
Definition at line 18 of file lpcVIC.h.
| union { ... } |
| union { ... } |
| REG32 vicRegs_t::_pad0[3] |
| REG32 vicRegs_t::_pad1[50] |
| REG32 vicRegs_t::_pad2[48] |
| REG32 vicRegs_t::defVectAddr |
| REG32 vicRegs_t::fiqStatus |
| REG32 vicRegs_t::intEnable |
| REG32 vicRegs_t::intEnClear |
| REG32 vicRegs_t::intSelect |
| REG32 vicRegs_t::irqStatus |
| REG32 vicRegs_t::protection |
| REG32 vicRegs_t::rawIntr |
| REG32 vicRegs_t::softInt |
| REG32 vicRegs_t::softIntClear |
| REG32 vicRegs_t::vectAddr |
| REG32 vicRegs_t::vectAddr0 |
| REG32 vicRegs_t::vectAddr1 |
| REG32 vicRegs_t::vectAddr10 |
| REG32 vicRegs_t::vectAddr11 |
| REG32 vicRegs_t::vectAddr12 |
| REG32 vicRegs_t::vectAddr13 |
| REG32 vicRegs_t::vectAddr14 |
| REG32 vicRegs_t::vectAddr15 |
| REG32 vicRegs_t::vectAddr2 |
| REG32 vicRegs_t::vectAddr3 |
| REG32 vicRegs_t::vectAddr4 |
| REG32 vicRegs_t::vectAddr5 |
| REG32 vicRegs_t::vectAddr6 |
| REG32 vicRegs_t::vectAddr7 |
| REG32 vicRegs_t::vectAddr8 |
| REG32 vicRegs_t::vectAddr9 |
| REG32 vicRegs_t::vectAdrArray[16] |
| REG32 vicRegs_t::vectCntl0 |
| REG32 vicRegs_t::vectCntl1 |
| REG32 vicRegs_t::vectCntl10 |
| REG32 vicRegs_t::vectCntl11 |
| REG32 vicRegs_t::vectCntl12 |
| REG32 vicRegs_t::vectCntl13 |
| REG32 vicRegs_t::vectCntl14 |
| REG32 vicRegs_t::vectCntl15 |
| REG32 vicRegs_t::vectCntl2 |
| REG32 vicRegs_t::vectCntl3 |
| REG32 vicRegs_t::vectCntl4 |
| REG32 vicRegs_t::vectCntl5 |
| REG32 vicRegs_t::vectCntl6 |
| REG32 vicRegs_t::vectCntl7 |
| REG32 vicRegs_t::vectCntl8 |
| REG32 vicRegs_t::vectCntl9 |
| REG32 vicRegs_t::vectCtlArray[16] |
1.4.7