00001 /* 00002 * $Id: pll.c,v 1 2004/11/12 14:18:00 BorisK Exp $ 00003 * 00004 * Copyright (C) 2004 ONTRACK s.r.o. 00005 * 00006 * This program is free software; you can redistribute it and/or 00007 * modify it under the terms of the GNU General Public License 00008 * as published by the Free Software Foundation; either version 2 00009 * of the License, or (at your option) any later version. 00010 * 00011 * This program is distributed in the hope that it will be useful, 00012 * but WITHOUT ANY WARRANTY; without even the implied warranty of 00013 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00014 * GNU General Public License for more details. 00015 * 00016 * You should have received a copy of the GNU General Public License 00017 * along with this program; if not, write to the Free Software 00018 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 00019 * 02111-1307, USA. 00020 * 00021 * [1] ARM-based Microcontroller LPC2119/2129/2194/2292/9994, "Preliminary User Manual", February -3, 2004 00022 * 00023 * Written by Boris Kralik <kralikbo@yahoo.com>, 2004. 00024 * 00025 */ 00026 #include "pll.h" 00027 /* [1] page 78 00028 Fosc = 24MHz 24MHz 00029 pclk = 12MHz 00030 Fcco = 192MHz 00031 cclk = M*Fosc = 24 MHz; cclk=Fcco/(2*P)= 24MHz 00032 M = PLLCFG 4:0 = 24MHz / 24MHz = 1 ;(1 - 1) to PLLCFG 4:0 00033 P = PLLCFG 6:5 Fcco/(cclk*2) Fcco = 192 MHz, P=192MHz/(2*48MHz) = 2 00034 */ 00035 void PLLSet(void) // PLLCON, PLLCFG, PLLSTAT, PLLFEED 00036 { // ???? nejde mi zapnut PLL - PLLE a PLLC nesmie byt 1 00037 //SCB_VPBDIV = 0x02; // VPB bus clock is one half of the processor clock 9600Baud 00038 SCB_VPBDIV = 0x02; // 19200Baud 00039 // SCB_PLLCON &= 0xFC; // xxxx xx00 = 0xFC - turn off PLL 00040 SCB_PLLCON |= 0x02; // PLLE = 1, PLLC = 1 turn on PLL 00041 00042 SCB_PLLCFG = 0x21; // 10 00000 <> M=2 P=2 00043 00044 SCB_PLLFEED = 0xAA; // PLL Valid sequence 00045 SCB_PLLFEED = 0x55; 00046 }
1.4.7