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Defines | |
| #define | TIR_MR0I (1 << 0) |
| #define | TIR_MR1I (1 << 1) |
| #define | TIR_MR2I (1 << 2) |
| #define | TIR_MR3I (1 << 3) |
| #define | TIR_CR0I (1 << 4) |
| #define | TIR_CR1I (1 << 5) |
| #define | TIR_CR2I (1 << 6) |
| #define | TIR_CR3I (1 << 7) |
| #define | PWMIR_MR0I (1 << 0) |
| #define | PWMIR_MR1I (1 << 1) |
| #define | PWMIR_MR2I (1 << 2) |
| #define | PWMIR_MR3I (1 << 3) |
| #define | PWMIR_MR4I (1 << 8) |
| #define | PWMIR_MR5I (1 << 9) |
| #define | PWMIR_MR6I (1 << 10) |
| #define | PWMIR_MASK (0x070F) |
| #define | TCR_ENABLE (1 << 0) |
| #define | TCR_RESET (1 << 1) |
| #define | PWMCR_ENABLE (1 << 0) |
| #define | PWMCR_RESET (1 << 1) |
| #define | TMCR_MR0_I (1 << 0) |
| #define | TMCR_MR0_R (1 << 1) |
| #define | TMCR_MR0_S (1 << 2) |
| #define | TMCR_MR1_I (1 << 3) |
| #define | TMCR_MR1_R (1 << 4) |
| #define | TMCR_MR1_S (1 << 5) |
| #define | TMCR_MR2_I (1 << 6) |
| #define | TMCR_MR2_R (1 << 7) |
| #define | TMCR_MR2_S (1 << 8) |
| #define | TMCR_MR3_I (1 << 9) |
| #define | TMCR_MR3_R (1 << 10) |
| #define | TMCR_MR3_S (1 << 11) |
| #define | TCCR_CR0_R (1 << 0) |
| #define | TCCR_CR0_F (1 << 1) |
| #define | TCCR_CR0_I (1 << 2) |
| #define | TCCR_CR1_R (1 << 3) |
| #define | TCCR_CR1_F (1 << 4) |
| #define | TCCR_CR1_I (1 << 5) |
| #define | TCCR_CR2_R (1 << 6) |
| #define | TCCR_CR2_F (1 << 7) |
| #define | TCCR_CR2_I (1 << 8) |
| #define | TCCR_CR3_R (1 << 9) |
| #define | TCCR_CR3_F (1 << 10) |
| #define | TCCR_CR3_I (1 << 11) |
1.4.7