00001 /****************************************************************************** 00002 * 00003 * $RCSfile: $ 00004 * $Revision: $ 00005 * 00006 * Header file for Philips LPC ARM Processors. 00007 * Copyright 2004 R O SoftWare 00008 * 00009 * No guarantees, warrantees, or promises, implied or otherwise. 00010 * May be used for hobby or commercial purposes provided copyright 00011 * notice remains intact. 00012 * 00013 *****************************************************************************/ 00014 #ifndef INC_LPC_SCB_H 00015 #define INC_LPC_SCB_H 00016 00018 // MAM defines 00019 #define MAMCR_OFF 0 00020 #define MAMCR_PART 1 00021 #define MAMCR_FULL 2 00022 00023 #define MAMTIM_CYCLES (((CCLK) + 19999999) / 20000000) 00024 00026 // MEMMAP defines 00027 #define MEMMAP_BBLK 0 // Interrupt Vectors in Boot Block 00028 #define MEMMAP_FLASH 1 // Interrupt Vectors in Flash 00029 #define MEMMAP_SRAM 2 // Interrupt Vectors in SRAM 00030 00032 // PLL defines & computations 00033 // Compute the value of PLL_DIV and test range validity 00034 // FOSC & PLL_MUL should be defined in project configuration file (config.h) 00035 //#ifndef CCLK 00036 //#define CCLK (FOSC * PLL_MUL) // CPU Clock Freq. 00037 //#endif 00038 // 00039 //#define FCCO_MAX (320000000) // Max CC Osc Freq. 00040 //#define PLL_DIV 2 //(FCCO_MAX / (2 * CCLK)) // PLL Divider 00041 //#define FCCO (FOSC * PLL_MUL * 2 * PLL_DIV) // CC Osc. Freq. 00042 00043 // PLLCON Register Bit Definitions 00044 #define PLLCON_PLLE (1 << 0) // PLL Enable 00045 #define PLLCON_PLLC (1 << 1) // PLL Connect 00046 00047 // PLLCFG Register Bit Definitions 00048 #define PLLCFG_MSEL ((PLL_MUL - 1) << 0) // PLL Multiplier 00049 #define PLLCFG_PSEL ((PLL_DIV - 1) << 5) // PLL Divider 00050 00051 // PLLSTAT Register Bit Definitions 00052 #define PLLSTAT_LOCK (1 << 10) // PLL Lock Status Bit 00053 00055 // VPBDIV defines & computations 00056 #define VPBDIV_VALUE (PBSD & 0x03) // VPBDIV value 00057 00058 #endif
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