example1: projekty/Source/example1/src/include/lpc2100/lpc22xx.h Source File

00001 /******************************************************************************
00002  *
00003  * $RCSfile: $
00004  * $Revision: $
00005  *
00006  * Header file for Philips LPC22xx ARM Processors 
00007  * Copyright 2004 R O SoftWare
00008  *
00009  * No guarantees, warrantees, or promises, implied or otherwise.
00010  * May be used for hobby or commercial purposes provided copyright
00011  * notice remains intact.
00012  *
00013  *****************************************************************************/
00014 #ifndef INC_LPC22xx_H
00015 #define INC_LPC22xx_H
00016 
00017 #define REG_8           volatile unsigned char
00018 #define REG16           volatile unsigned short
00019 #define REG32           volatile unsigned long
00020 
00021 #include "lpc2100/lpcWD.h"
00022 #include "lpc2100/lpcTMR.h"
00023 #include "lpc2100/lpcUART.h"
00024 #include "lpc2100/lpcI2C.h"
00025 #include "lpc2100/lpcSPI.h"
00026 #include "lpc2100/lpcRTC.h"
00027 #include "lpc2100/lpcGPIO.h"
00028 #include "lpc2100/lpcPIN.h"
00029 #include "lpc2100/lpcADC.h"
00030 #include "lpc2100/lpcSCB.h"
00031 #include "lpc2100/lpcEMC.h"
00032 #include "lpc2100/lpcVIC.h"
00033 
00035 // Watchdog
00036 #define WD              ((wdRegs_t *)0xE0000000)
00037 
00038 // Watchdog Registers
00039 #define WDMOD           WD->mod         /* Watchdog Mode Register */
00040 #define WDTC            WD->tc          /* Watchdog Time Constant Register */
00041 #define WDFEED          WD->feed        /* Watchdog Feed Register */
00042 #define WDTV            WD->tv          /* Watchdog Time Value Register */
00043 
00045 // Timer 0
00046 #define TMR0            ((pwmTmrRegs_t *)0xE0004000)
00047 
00048 // Timer 0 Registers
00049 #define T0IR            TMR0->ir        /* Interrupt Register */
00050 #define T0TCR           TMR0->tcr       /* Timer Control Register */
00051 #define T0TC            TMR0->tc        /* Timer Counter */
00052 #define T0PR            TMR0->pr        /* Prescale Register */
00053 #define T0PC            TMR0->pc        /* Prescale Counter Register */
00054 #define T0MCR           TMR0->mcr       /* Match Control Register */
00055 #define T0MR0           TMR0->mr0       /* Match Register 0 */
00056 #define T0MR1           TMR0->mr1       /* Match Register 1 */
00057 #define T0MR2           TMR0->mr2       /* Match Register 2 */
00058 #define T0MR3           TMR0->mr3       /* Match Register 3 */
00059 #define T0CCR           TMR0->ccr       /* Capture Control Register */
00060 #define T0CR0           TMR0->cr0       /* Capture Register 0 */
00061 #define T0CR1           TMR0->cr1       /* Capture Register 1 */
00062 #define T0CR2           TMR0->cr2       /* Capture Register 2 */
00063 #define T0CR3           TMR0->cr3       /* Capture Register 3 */
00064 #define T0EMR           TMR0->emr       /* External Match Register */
00065 
00067 // Timer 1
00068 #define TMR1            ((pwmTmrRegs_t *)0xE0008000)
00069 
00070 // Timer 1 Registers
00071 #define T1IR            TMR1->ir        /* Interrupt Register */
00072 #define T1TCR           TMR1->tcr       /* Timer Control Register */
00073 #define T1TC            TMR1->tc        /* Timer Counter */
00074 #define T1PR            TMR1->pr        /* Prescale Register */
00075 #define T1PC            TMR1->pc        /* Prescale Counter Register */
00076 #define T1MCR           TMR1->mcr       /* Match Control Register */
00077 #define T1MR0           TMR1->mr0       /* Match Register 0 */
00078 #define T1MR1           TMR1->mr1       /* Match Register 1 */
00079 #define T1MR2           TMR1->mr2       /* Match Register 2 */
00080 #define T1MR3           TMR1->mr3       /* Match Register 3 */
00081 #define T1CCR           TMR1->ccr       /* Capture Control Register */
00082 #define T1CR0           TMR1->cr0       /* Capture Register 0 */
00083 #define T1CR1           TMR1->cr1       /* Capture Register 1 */
00084 #define T1CR2           TMR1->cr2       /* Capture Register 2 */
00085 #define T1CR3           TMR1->cr3       /* Capture Register 3 */
00086 #define T1EMR           TMR1->emr       /* External Match Register */
00087 
00089 // Pulse Width Modulator (PWM)
00090 #define PWM             ((pwmTmrRegs_t *)0xE0014000)
00091 
00092 // PWM Registers
00093 #define PWMIR           PWM->ir         /* Interrupt Register */
00094 #define PWMTCR          PWM->tcr        /* Timer Control Register */
00095 #define PWMTC           PWM->tc         /* Timer Counter */
00096 #define PWMPR           PWM->pr         /* Prescale Register */
00097 #define PWMPC           PWM->pc         /* Prescale Counter Register */
00098 #define PWMMCR          PWM->mcr        /* Match Control Register */
00099 #define PWMMR0          PWM->mr0        /* Match Register 0 */
00100 #define PWMMR1          PWM->mr1        /* Match Register 1 */
00101 #define PWMMR2          PWM->mr2        /* Match Register 2 */
00102 #define PWMMR3          PWM->mr3        /* Match Register 3 */
00103 #define PWMMR4          PWM->mr4        /* Match Register 4 */
00104 #define PWMMR5          PWM->mr5        /* Match Register 5 */
00105 #define PWMMR6          PWM->mr6        /* Match Register 6 */
00106 #define PWMPCR          PWM->pcr        /* Control Register */
00107 #define PWMLER          PWM->ler        /* Latch Enable Register */
00108 
00110 // Universal Asynchronous Receiver Transmitter 0 (UART0)
00111 #define UART0           ((uartRegs_t *)0xE000C000)
00112 #define U0_PINSEL       (0x00000005)    /* PINSEL0 Value for UART0 */
00113 #define U0_PINMASK      (0x0000000F)    /* PINSEL0 Mask for UART0 */
00114 
00115 // UART0 Registers
00116 #define U0RBR           UART0->rbr      /* Receive Buffer Register */
00117 #define U0THR           UART0->thr      /* Transmit Holding Register */
00118 #define U0IER           UART0->ier      /* Interrupt Enable Register */
00119 #define U0IIR           UART0->iir      /* Interrupt ID Register */
00120 #define U0FCR           UART0->fcr      /* FIFO Control Register */
00121 #define U0LCR           UART0->lcr      /* Line Control Register */
00122 #define U0LSR           UART0->lsr      /* Line Status Register */
00123 #define U0SCR           UART0->scr      /* Scratch Pad Register */
00124 #define U0DLL           UART0->dll      /* Divisor Latch Register (LSB) */
00125 #define U0DLM           UART0->dlm      /* Divisor Latch Register (MSB) */
00126 
00128 // Universal Asynchronous Receiver Transmitter 1 (UART1)
00129 #define UART1           ((uartRegs_t *)0xE0010000)
00130 #define U1_PINSEL       (0x00050000)    /* PINSEL0 Value for UART1 */
00131 #define U1_PINMASK      (0x000F0000)    /* PINSEL0 Mask for UART1 */
00132 
00133 // UART1 Registers
00134 #define U1RBR           UART1->rbr      /* Receive Buffer Register */
00135 #define U1THR           UART1->thr      /* Transmit Holding Register */
00136 #define U1IER           UART1->ier      /* Interrupt Enable Register */
00137 #define U1IIR           UART1->iir      /* Interrupt ID Register */
00138 #define U1FCR           UART1->fcr      /* FIFO Control Register */
00139 #define U1LCR           UART1->lcr      /* Line Control Register */
00140 #define U1MCR           UART1->mcr      /* MODEM Control Register */
00141 #define U1LSR           UART1->lsr      /* Line Status Register */
00142 #define U1MSR           UART1->msr      /* MODEM Status Register */
00143 #define U1SCR           UART1->scr      /* Scratch Pad Register */
00144 #define U1DLL           UART1->dll      /* Divisor Latch Register (LSB) */
00145 #define U1DLM           UART1->dlm      /* Divisor Latch Register (MSB) */
00146 
00148 // I2C Interface
00149 #define I2C             ((i2cRegs_t *)0xE001C000)
00150 
00151 // I2C Registers
00152 #define I2CONSET        I2C->conset     /* Control Set Register */
00153 #define I2STAT          I2C->stat       /* Status Register */
00154 #define I2DAT           I2C->dat        /* Data Register */
00155 #define I2ADR           I2C->adr        /* Slave Address Register */
00156 #define I2SCLH          I2C->sclh       /* SCL Duty Cycle Register (high half word) */
00157 #define I2SCLL          I2C->scll       /* SCL Duty Cycle Register (low half word) */
00158 #define I2CONCLR        I2C->conclr     /* Control Clear Register */
00159 
00161 // Serial Peripheral Interface 0 (SPI0)
00162 #define SPI0            ((spiRegs_t *)0xE0020000)
00163 
00164 // SPI0 Registers
00165 #define S0SPCR          SPI0->cr        /* Control Register */
00166 #define S0SPSR          SPI0->sr        /* Status Register */
00167 #define S0SPDR          SPI0->dr        /* Data Register */
00168 #define S0SPCCR         SPI0->ccr       /* Clock Counter Register */
00169 #define S0SPINT         SPI0->flag      /* Interrupt Flag Register */
00170 
00172 // Serial Peripheral Interface 1 (SPI1)
00173 #define SPI1            ((spiRegs_t *)0xE0030000)
00174 
00175 // SPI1 Registers
00176 #define S1SPCR          SPI1->cr        /* Control Register */
00177 #define S1SPSR          SPI1->sr        /* Status Register */
00178 #define S1SPDR          SPI1->dr        /* Data Register */
00179 #define S1SPCCR         SPI1->ccr       /* Clock Counter Register */
00180 #define S1SPINT         SPI1->flag      /* Interrupt Flag Register */
00181 
00183 // Real Time Clock
00184 #define RTC             ((rtcRegs_t *)0xE0024000)
00185 
00186 // RTC Registers
00187 #define RTCILR          RTC->ilr        /* Interrupt Location Register */
00188 #define RTCCTC          RTC->ctc        /* Clock Tick Counter */
00189 #define RTCCCR          RTC->ccr        /* Clock Control Register */
00190 #define RTCCIIR         RTC->ciir       /* Counter Increment Interrupt Register */
00191 #define RTCAMR          RTC->amr        /* Alarm Mask Register */
00192 #define RTCCTIME0       RTC->ctime0     /* Consolidated Time Register 0 */
00193 #define RTCCTIME1       RTC->ctime1     /* Consolidated Time Register 1 */
00194 #define RTCCTIME2       RTC->ctime2     /* Consolidated Time Register 2 */
00195 #define RTCSEC          RTC->sec        /* Seconds Register */
00196 #define RTCMIN          RTC->min        /* Minutes Register */
00197 #define RTCHOUR         RTC->hour       /* Hours Register */
00198 #define RTCDOM          RTC->dom        /* Day Of Month Register */
00199 #define RTCDOW          RTC->dow        /* Day Of Week Register */
00200 #define RTCDOY          RTC->doy        /* Day Of Year Register */
00201 #define RTCMONTH        RTC->month      /* Months Register */
00202 #define RTCYEAR         RTC->year       /* Years Register */
00203 #define RTCALSEC        RTC->alsec      /* Alarm Seconds Register */
00204 #define RTCALMIN        RTC->almin      /* Alarm Minutes Register */
00205 #define RTCALHOUR       RTC->alhour     /* Alarm Hours Register */
00206 #define RTCALDOM        RTC->aldom      /* Alarm Day Of Month Register */
00207 #define RTCALDOW        RTC->aldow      /* Alarm Day Of Week Register */
00208 #define RTCALDOY        RTC->aldoy      /* Alarm Day Of Year Register */
00209 #define RTCALMON        RTC->almon      /* Alarm Months Register */
00210 #define RTCALYEAR       RTC->alyear     /* Alarm Years Register */
00211 #define RTCPREINT       RTC->preint     /* Prescale Value Register (integer) */
00212 #define RTCPREFRAC      RTC->prefrac    /* Prescale Value Register (fraction) */
00213 
00215 // General Purpose Input/Output
00216 #define GPIO0           ((gpioRegs_t *)0xE0028000)
00217 #define GPIO1           ((gpioRegs_t *)0xE0028010)
00218 #define GPIO2           ((gpioRegs_t *)0xE0028020)
00219 #define GPIO3           ((gpioRegs_t *)0xE0028030)
00220 
00221 // GPIO Registers
00222 #define IO0PIN          GPIO0->in       /* P0 Pin Value Register */
00223 #define IO0SET          GPIO0->set      /* P0 Pin Output Set Register */
00224 #define IO0DIR          GPIO0->dir      /* P0 Pin Direction Register */
00225 #define IO0CLR          GPIO0->clr      /* P0 Pin Output Clear Register */
00226 #define IO1PIN          GPIO1->in       /* P1 Pin Value Register */
00227 #define IO1SET          GPIO1->set      /* P1 Pin Output Set Register */
00228 #define IO1DIR          GPIO1->dir      /* P1 Pin Direction Register */
00229 #define IO1CLR          GPIO1->clr      /* P1 Pin Output Clear Register */
00230 #define IO2PIN          GPIO2->in       /* P2 Pin Value Register */
00231 #define IO2SET          GPIO2->set      /* P2 Pin Output Set Register */
00232 #define IO2DIR          GPIO2->dir      /* P2 Pin Direction Register */
00233 #define IO2CLR          GPIO2->clr      /* P2 Pin Output Clear Register */
00234 #define IO3PIN          GPIO3->in       /* P3 Pin Value Register */
00235 #define IO3SET          GPIO3->set      /* P3 Pin Output Set Register */
00236 #define IO3DIR          GPIO3->dir      /* P3 Pin Direction Register */
00237 #define IO3CLR          GPIO3->clr      /* P3 Pin Output Clear Register */
00238 
00240 // Pin Connect Block
00241 #define PINSEL          ((pinRegs_t *)0xE002C000)
00242 
00243 // Pin Connect Block Registers
00244 #define PINSEL0         PINSEL->sel0    /* Pin Function Select Register 0 */
00245 #define PINSEL1         PINSEL->sel1    /* Pin Function Select Register 1 */
00246 #define PINSEL2         PINSEL->sel2    /* Pin Function Select Register 2 */
00247 
00249 // A/D Converter
00250 #define ADC             ((adcRegs_t *)0xE0034000)
00251 
00252 // A/D Converter Registers
00253 #define ADCR            ADC->cr         /* Control Register */
00254 #define ADDR            ADC->dr         /* Data Register */
00255 
00257 // System Contol Block
00258 #define SCB             ((scbRegs_t *)0xE01FC000)
00259 
00260 // Memory Accelerator Module Registers (MAM)
00261 #define MAMCR           SCB->mam.cr     /* Control Register */
00262 #define MAMTIM          SCB->mam.tim    /* Timing Control Register */
00263 
00264 // Memory Mapping Control Register
00265 #define MEMMAP          SCB->memmap
00266 
00267 // Phase Locked Loop Registers (PLL)
00268 #define PLLCON          SCB->pll.con    /* Control Register */
00269 #define PLLCFG          SCB->pll.cfg    /* Configuration Register */
00270 #define PLLSTAT         SCB->pll.stat   /* Status Register */
00271 #define PLLFEED         SCB->pll.feed   /* Feed Register */
00272 
00273 // Power Control Registers
00274 #define PCON            SCB->p.con      /* Control Register */
00275 #define PCONP           SCB->p.conp     /* Peripherals Register */
00276 
00277 // VPB Divider Register
00278 #define VPBDIV          SCB->vpbdiv
00279 
00280 // External Interrupt Registers
00281 #define EXTINT          SCB->ext.flag   /* Flag Register */
00282 #define EXTWAKE         SCB->ext.wake   /* Wakeup Register */
00283 #define EXTMODE         SCB->ext.mode   /* Mode Register */
00284 #define EXTPOLAR        SCB->ext.polar  /* Polarity Register */
00285 
00287 // External Memory Controller (EMC)
00288 #define EMC             ((emcRegs_t *)0xFFE00000)
00289 
00290 // External Memory Controller Registers
00291 #define BCFG0           EMC->bcfg0      /* Bank 0 Configuration Register */
00292 #define BCFG1           EMC->bcfg1      /* Bank 1 Configuration Register */
00293 #define BCFG2           EMC->bcfg2      /* Bank 2 Configuration Register */
00294 #define BCFG3           EMC->bcfg3      /* Bank 3 Configuration Register */
00295 
00297 // Vectored Interrupt Controller
00298 #define VIC             ((vicRegs_t *)0xFFFFF000)
00299 
00300 // Vectored Interrupt Controller Registers
00301 #define VICIRQStatus    VIC->irqStatus  /* IRQ Status Register */
00302 #define VICFIQStatus    VIC->fiqStatus  /* FIQ Status Register */
00303 #define VICRawIntr      VIC->rawIntr    /* Raw Interrupt Status Register */
00304 #define VICIntSelect    VIC->intSelect  /* Interrupt Select Register */
00305 #define VICIntEnable    VIC->intEnable  /* Interrupt Enable Register */
00306 #define VICIntEnClear   VIC->intEnClear /* Interrupt Enable Clear Register */
00307 #define VICSoftInt      VIC->softInt    /* Software Interrupt Register */
00308 #define VICSoftIntClear VIC->softIntClear /* Software Interrupt Clear Register */
00309 #define VICProtection   VIC->protection /* Protection Enable Register */
00310 #define VICVectAddr     VIC->vectAddr   /* Vector Address Register */
00311 #define VICDefVectAddr  VIC->defVectAddr /* Default Vector Address Register */
00312 #define VICVectAddr0    VIC->vectAddr0  /* Vector Address 0 Register */
00313 #define VICVectAddr1    VIC->vectAddr1  /* Vector Address 1 Register */
00314 #define VICVectAddr2    VIC->vectAddr2  /* Vector Address 2 Register */
00315 #define VICVectAddr3    VIC->vectAddr3  /* Vector Address 3 Register */
00316 #define VICVectAddr4    VIC->vectAddr4  /* Vector Address 4 Register */
00317 #define VICVectAddr5    VIC->vectAddr5  /* Vector Address 5 Register */
00318 #define VICVectAddr6    VIC->vectAddr6  /* Vector Address 6 Register */
00319 #define VICVectAddr7    VIC->vectAddr7  /* Vector Address 7 Register */
00320 #define VICVectAddr8    VIC->vectAddr8  /* Vector Address 8 Register */
00321 #define VICVectAddr9    VIC->vectAddr9  /* Vector Address 9 Register */
00322 #define VICVectAddr10   VIC->vectAddr10 /* Vector Address 10 Register */
00323 #define VICVectAddr11   VIC->vectAddr11 /* Vector Address 11 Register */
00324 #define VICVectAddr12   VIC->vectAddr12 /* Vector Address 12 Register */
00325 #define VICVectAddr13   VIC->vectAddr13 /* Vector Address 13 Register */
00326 #define VICVectAddr14   VIC->vectAddr14 /* Vector Address 14 Register */
00327 #define VICVectAddr15   VIC->vectAddr15 /* Vector Address 15 Register */
00328 #define VICVectAdrArray VIC->vectAdrArray /* Vector Address Register Array */
00329 #define VICVectCntl0    VIC->vectCntl0  /* Vector Control 0 Register */
00330 #define VICVectCntl1    VIC->vectCntl1  /* Vector Control 1 Register */
00331 #define VICVectCntl2    VIC->vectCntl2  /* Vector Control 2 Register */
00332 #define VICVectCntl3    VIC->vectCntl3  /* Vector Control 3 Register */
00333 #define VICVectCntl4    VIC->vectCntl4  /* Vector Control 4 Register */
00334 #define VICVectCntl5    VIC->vectCntl5  /* Vector Control 5 Register */
00335 #define VICVectCntl6    VIC->vectCntl6  /* Vector Control 6 Register */
00336 #define VICVectCntl7    VIC->vectCntl7  /* Vector Control 7 Register */
00337 #define VICVectCntl8    VIC->vectCntl8  /* Vector Control 8 Register */
00338 #define VICVectCntl9    VIC->vectCntl9  /* Vector Control 9 Register */
00339 #define VICVectCntl10   VIC->vectCntl10 /* Vector Control 10 Register */
00340 #define VICVectCntl11   VIC->vectCntl11 /* Vector Control 11 Register */
00341 #define VICVectCntl12   VIC->vectCntl12 /* Vector Control 12 Register */
00342 #define VICVectCntl13   VIC->vectCntl13 /* Vector Control 13 Register */
00343 #define VICVectCntl14   VIC->vectCntl14 /* Vector Control 14 Register */
00344 #define VICVectCntl15   VIC->vectCntl15 /* Vector Control 15 Register */
00345 #define VICVectCtlArray VIC->vectCtlArray /* Vector Control Register Array */
00346 
00347 #endif