example1: projekty/Source/example1/src/include/lpc2119.h Source File

00001 #ifndef lpc2119_h
00002 #define lpc2119_h
00003 /*******************************************************************************
00004 lpc2119.h - Register defs for Philips LPC 2119 / 2129 / 2290 / 2292 / 2294
00005 
00006 
00007 THE SOFTWARE IS DELIVERED "AS IS" WITHOUT WARRANTY OR CONDITION OF ANY KIND, 
00008 EITHER EXPRESS, IMPLIED OR STATUTORY. THIS INCLUDES WITHOUT LIMITATION ANY 
00009 WARRANTY OR CONDITION WITH RESPECT TO MERCHANTABILITY OR FITNESS FOR ANY 
00010 PARTICULAR PURPOSE, OR AGAINST THE INFRINGEMENTS OF INTELLECTUAL PROPERTY RIGHTS 
00011 OF OTHERS.
00012            
00013 This file may be freely used for commercial and non-commercial applications, 
00014 including being redistributed with any tools.
00015 
00016 If you find a problem with the file, please report it so that it can be fixed.
00017 
00018 Created by Sten Larsson (sten_larsson at yahoo com)
00019 *******************************************************************************/
00020 
00021 #define REG8  (volatile unsigned char*)
00022 #define REG16 (volatile unsigned short*)
00023 #define REG32 (volatile unsigned int*)
00024 
00025 
00026 /*##############################################################################
00027 ## MISC
00028 ##############################################################################*/
00029 
00030         /* Constants for data to put in IRQ/FIQ Exception Vectors */
00031 #define VECTDATA_IRQ  0xE51FFFF0  /* LDR PC,[PC,#-0xFF0] */
00032 #define VECTDATA_FIQ  /* __TODO */
00033 
00034 
00035 /*##############################################################################
00036 ## VECTORED INTERRUPT CONTROLLER
00037 ##############################################################################*/
00038 
00039 #define VICIRQStatus    (*(REG32 (0xFFFFF000)))
00040 #define VICFIQStatus    (*(REG32 (0xFFFFF004)))
00041 #define VICRawIntr      (*(REG32 (0xFFFFF008)))
00042 #define VICIntSelect    (*(REG32 (0xFFFFF00C)))
00043 #define VICIntEnable    (*(REG32 (0xFFFFF010)))
00044 #define VICIntEnClear   (*(REG32 (0xFFFFF014)))
00045 #define VICSoftInt      (*(REG32 (0xFFFFF018)))
00046 #define VICSoftIntClear (*(REG32 (0xFFFFF01C)))
00047 #define VICProtection   (*(REG32 (0xFFFFF020)))
00048 #define VICVectAddr     (*(REG32 (0xFFFFF030)))
00049 #define VICDefVectAddr  (*(REG32 (0xFFFFF034)))
00050 
00051 #define VICVectAddr0    (*(REG32 (0xFFFFF100)))
00052 #define VICVectAddr1    (*(REG32 (0xFFFFF104)))
00053 #define VICVectAddr2    (*(REG32 (0xFFFFF108)))
00054 #define VICVectAddr3    (*(REG32 (0xFFFFF10C)))
00055 #define VICVectAddr4    (*(REG32 (0xFFFFF110)))
00056 #define VICVectAddr5    (*(REG32 (0xFFFFF114)))
00057 #define VICVectAddr6    (*(REG32 (0xFFFFF118)))
00058 #define VICVectAddr7    (*(REG32 (0xFFFFF11C)))
00059 #define VICVectAddr8    (*(REG32 (0xFFFFF120)))
00060 #define VICVectAddr9    (*(REG32 (0xFFFFF124)))
00061 #define VICVectAddr10   (*(REG32 (0xFFFFF128)))
00062 #define VICVectAddr11   (*(REG32 (0xFFFFF12C)))
00063 #define VICVectAddr12   (*(REG32 (0xFFFFF130)))
00064 #define VICVectAddr13   (*(REG32 (0xFFFFF134)))
00065 #define VICVectAddr14   (*(REG32 (0xFFFFF138)))
00066 #define VICVectAddr15   (*(REG32 (0xFFFFF13C)))
00067 
00068 #define VICVectCntl0    (*(REG32 (0xFFFFF200)))
00069 #define VICVectCntl1    (*(REG32 (0xFFFFF204)))
00070 #define VICVectCntl2    (*(REG32 (0xFFFFF208)))
00071 #define VICVectCntl3    (*(REG32 (0xFFFFF20C)))
00072 #define VICVectCntl4    (*(REG32 (0xFFFFF210)))
00073 #define VICVectCntl5    (*(REG32 (0xFFFFF214)))
00074 #define VICVectCntl6    (*(REG32 (0xFFFFF218)))
00075 #define VICVectCntl7    (*(REG32 (0xFFFFF21C)))
00076 #define VICVectCntl8    (*(REG32 (0xFFFFF220)))
00077 #define VICVectCntl9    (*(REG32 (0xFFFFF224)))
00078 #define VICVectCntl10   (*(REG32 (0xFFFFF228)))
00079 #define VICVectCntl11   (*(REG32 (0xFFFFF22C)))
00080 #define VICVectCntl12   (*(REG32 (0xFFFFF230)))
00081 #define VICVectCntl13   (*(REG32 (0xFFFFF234)))
00082 #define VICVectCntl14   (*(REG32 (0xFFFFF238)))
00083 #define VICVectCntl15   (*(REG32 (0xFFFFF23C)))
00084 
00085 #define VICITCR         (*(REG32 (0xFFFFF300)))
00086 #define VICITIP1        (*(REG32 (0xFFFFF304)))
00087 #define VICITIP2        (*(REG32 (0xFFFFF308)))
00088 #define VICITOP1        (*(REG32 (0xFFFFF30C)))
00089 #define VICITOP2        (*(REG32 (0xFFFFF310)))
00090 #define VICPeriphID0    (*(REG32 (0xFFFFFFE0)))
00091 #define VICPeriphID1    (*(REG32 (0xFFFFFFE4)))
00092 #define VICPeriphID2    (*(REG32 (0xFFFFFFE8)))
00093 #define VICPeriphID3    (*(REG32 (0xFFFFFFEC)))
00094 
00095 #define VICIntEnClr     VICIntEnClear
00096 #define VICSoftIntClr   VICSoftIntClear
00097 
00098 
00099 /*##############################################################################
00100 ## PCB - Pin Connect Block
00101 ##############################################################################*/
00102 
00103 #define PCB_PINSEL0     (*(REG32 (0xE002C000)))
00104 #define PCB_PINSEL1     (*(REG32 (0xE002C004)))
00105 #define PCB_PINSEL2     (*(REG32 (0xE002C014)))
00106 
00107 
00108 /*##############################################################################
00109 ## GPIO - General Purpose I/O
00110 ##############################################################################*/
00111 
00112 #define GPIO0_IOPIN     (*(REG32 (0xE0028000)))
00113 #define GPIO0_IOSET     (*(REG32 (0xE0028004)))
00114 #define GPIO0_IODIR     (*(REG32 (0xE0028008)))
00115 #define GPIO0_IOCLR     (*(REG32 (0xE002800C)))
00116 
00117 #define GPIO1_IOPIN     (*(REG32 (0xE0028010)))
00118 #define GPIO1_IOSET     (*(REG32 (0xE0028014)))
00119 #define GPIO1_IODIR     (*(REG32 (0xE0028018)))
00120 #define GPIO1_IOCLR     (*(REG32 (0xE002801C)))
00121 
00122 #define GPIO2_IOPIN     (*(REG32 (0xE0028020)))
00123 #define GPIO2_IOSET     (*(REG32 (0xE0028024)))
00124 #define GPIO2_IODIR     (*(REG32 (0xE0028028)))
00125 #define GPIO2_IOCLR     (*(REG32 (0xE002802C)))
00126 
00127 #define GPIO3_IOPIN     (*(REG32 (0xE0028030)))
00128 #define GPIO3_IOSET     (*(REG32 (0xE0028034)))
00129 #define GPIO3_IODIR     (*(REG32 (0xE0028038)))
00130 #define GPIO3_IOCLR     (*(REG32 (0xE002803C)))
00131 
00132 
00133 /*##############################################################################
00134 ## UART0 / UART1
00135 ##############################################################################*/
00136 
00137 /* ---- UART 0 --------------------------------------------- */
00138 #define UART0_RBR       (*(REG32 (0xE000C000)))
00139 #define UART0_THR       (*(REG32 (0xE000C000)))
00140 #define UART0_IER       (*(REG32 (0xE000C004)))
00141 #define UART0_IIR       (*(REG32 (0xE000C008)))
00142 #define UART0_FCR       (*(REG32 (0xE000C008)))
00143 #define UART0_LCR       (*(REG32 (0xE000C00C)))
00144 #define UART0_LSR       (*(REG32 (0xE000C014)))
00145 #define UART0_SCR       (*(REG32 (0xE000C01C)))
00146 #define UART0_DLL       (*(REG32 (0xE000C000)))
00147 #define UART0_DLM       (*(REG32 (0xE000C004)))
00148 
00149 /* ---- UART 1 --------------------------------------------- */
00150 #define UART1_RBR       (*(REG32 (0xE0010000)))
00151 #define UART1_THR       (*(REG32 (0xE0010000)))
00152 #define UART1_IER       (*(REG32 (0xE0010004)))
00153 #define UART1_IIR       (*(REG32 (0xE0010008)))
00154 #define UART1_FCR       (*(REG32 (0xE0010008)))
00155 #define UART1_LCR       (*(REG32 (0xE001000C)))
00156 #define UART1_LSR       (*(REG32 (0xE0010014)))
00157 #define UART1_SCR       (*(REG32 (0xE001001C)))
00158 #define UART1_DLL       (*(REG32 (0xE0010000)))
00159 #define UART1_DLM       (*(REG32 (0xE0010004)))
00160 #define UART1_MCR       (*(REG32 (0xE0010010)))
00161 #define UART1_MSR       (*(REG32 (0xE0010018)))
00162 
00163 
00164 /*##############################################################################
00165 ## I2C
00166 ##############################################################################*/
00167 
00168 #define I2C_I2CONSET    (*(REG32 (0xE001C000)))
00169 #define I2C_I2STAT      (*(REG32 (0xE001C004)))
00170 #define I2C_I2DAT       (*(REG32 (0xE001C008)))
00171 #define I2C_I2ADR       (*(REG32 (0xE001C00C)))
00172 #define I2C_I2SCLH      (*(REG32 (0xE001C010)))
00173 #define I2C_I2SCLL      (*(REG32 (0xE001C014)))
00174 #define I2C_I2CONCLR    (*(REG32 (0xE001C018)))
00175 
00176 
00177 /*##############################################################################
00178 ## SPI - Serial Peripheral Interface 
00179 ##############################################################################*/
00180 
00181 #define SPI_SPCR        (*(REG32 (0xE0020000)))  /* SPI = SPI0 */
00182 #define SPI_SPSR        (*(REG32 (0xE0020004)))
00183 #define SPI_SPDR        (*(REG32 (0xE0020008)))
00184 #define SPI_SPCCR       (*(REG32 (0xE002000C)))
00185 #define SPI_SPTCR       (*(REG32 (0xE0020010)))
00186 #define SPI_SPTSR       (*(REG32 (0xE0020014)))
00187 #define SPI_SPTOR       (*(REG32 (0xE0020018)))
00188 #define SPI_SPINT       (*(REG32 (0xE002001C)))
00189 
00190 #define SPI0_SPCR       (*(REG32 (0xE0020000)))  /* SPI = SPI0 */
00191 #define SPI0_SPSR       (*(REG32 (0xE0020004)))
00192 #define SPI0_SPDR       (*(REG32 (0xE0020008)))
00193 #define SPI0_SPCCR      (*(REG32 (0xE002000C)))
00194 #define SPI0_SPTCR      (*(REG32 (0xE0020010)))
00195 #define SPI0_SPTSR      (*(REG32 (0xE0020014)))
00196 #define SPI0_SPTOR      (*(REG32 (0xE0020018)))
00197 #define SPI0_SPINT      (*(REG32 (0xE002001C)))
00198 
00199 #define SPI1_SPCR       (*(REG32 (0xE0030000)))
00200 #define SPI1_SPSR       (*(REG32 (0xE0030004)))
00201 #define SPI1_SPDR       (*(REG32 (0xE0030008)))
00202 #define SPI1_SPCCR      (*(REG32 (0xE003000C)))
00203 #define SPI1_SPTCR      (*(REG32 (0xE0030010)))
00204 #define SPI1_SPTSR      (*(REG32 (0xE0030014)))
00205 #define SPI1_SPTOR      (*(REG32 (0xE0030018)))
00206 #define SPI1_SPINT      (*(REG32 (0xE003001C)))
00207 
00208 
00209 /*##############################################################################
00210 ## CAN - CAN controllers and acceptance filter
00211 ##############################################################################*/
00212 
00213 /* TODO - add definitions for CAN */
00214 #define CAN_AFMR        ((*(REG32 (0xE003C000))))       //Acceptance Filter Register
00215 #define CAN_SFF         ((*(REG32 (0xE003C004))))       //Standard Frame Individual Start Address Register
00216 #define CAN_SFFGRP      ((*(REG32 (0xE003C008))))       //Standard Frame Group Start Address Register
00217 #define CAN_EFF         ((*(REG32 (0xE003C00C))))       //Extended Frame Start Address Register 
00218 #define CAN_EFFGRP      ((*(REG32 (0xE003C010))))       //Extended Frame Group Start Address Register
00219 #define CAN_EOF         ((*(REG32 (0xE003C014))))       //End of AF Table register
00220 #define CAN_LUT         ((*(REG32 (0xE003C018))))       //LUT Error Address register
00221 #define CAN_LUTERR      ((*(REG32 (0xE003C01C))))       //LUT Error Register
00222 #define CAN_TxSR        ((*(REG32 (0xE0040000))))       //CAN Central Transmit Status Register
00223 #define CAN_RxSR        ((*(REG32 (0xE0040004))))       //CAN Central Receive Status Register
00224 #define CAN_MSR         ((*(REG32 (0xE0040008))))       //CAN Central Miscellaneous Register
00225 /*##############################################################################
00226 ## CNAN1 and CAN2
00227 ##############################################################################*/
00228 #define CAN1_MOD        ((*(REG32 (0xE0044000))))       //Control and operating mode of the CAN Controller
00229 #define CAN1_CMR        ((*(REG32 (0xE0044004))))       //Command bits that affect the state of CAN Controller
00230 #define CAN1_GSR        ((*(REG32 (0xE0044008))))       //Global Controller Status and Error Counters
00231 #define CAN1_ICR        ((*(REG32 (0xE004400C))))       //Interrupt status, Arbitration Lost Capture, Error Code Capture
00232 #define CAN1_IER        ((*(REG32 (0xE0044010))))       //Interrupt Enable
00233 #define CAN1_BTR        ((*(REG32 (0xE0044014))))       //Bus Timing
00234 #define CAN1_EWL        ((*(REG32 (0xE0044018))))       //Error Warning Limit
00235 #define CAN1_SR         ((*(REG32 (0xE004401C))))       //Status Register
00236 #define CAN1_RFS        ((*(REG32 (0xE0044020))))       //Receive frame status
00237 #define CAN1_RID        ((*(REG32 (0xE0044024))))       //Received Identifier
00238 #define CAN1_RDA        ((*(REG32 (0xE0044028))))       //Received data bytes 1-4
00239 #define CAN1_RDB        ((*(REG32 (0xE004402C))))       //Received data bytes 5-8
00240 #define CAN1_TFI1       ((*(REG32 (0xE0044030))))       //Transmit frame info (1)
00241 #define CAN1_TID1       ((*(REG32 (0xE0044034))))       //Transmit identifier (1)
00242 #define CAN1_TDA1       ((*(REG32 (0xE0044038))))       //Transmit data bytes 1-4 (1)
00243 #define CAN1_TDB1       ((*(REG32 (0xE004403C))))       //Transmit data bytes 5-8 (1)
00244 #define CAN1_TFI2       ((*(REG32 (0xE0044040))))       //Transmit Frame info (2)
00245 #define CAN1_TID2       ((*(REG32 (0xE0044044))))       //Transmit identifier (2)
00246 #define CAN1_TDA2       ((*(REG32 (0xE0044048))))       //Transmit data bytes 1-4 (2)
00247 #define CAN1_TDB2       ((*(REG32 (0xE004404C))))       //Transmit data bytes 5-8 (2)
00248 #define CAN1_TFI3       ((*(REG32 (0xE0044050))))       //Transmit frame info (3)
00249 #define CAN1_TID3       ((*(REG32 (0xE0044054))))       //Transmit identifier (3)
00250 #define CAN1_TDA3       ((*(REG32 (0xE0044058))))       //Transmit data bytes 1-4 (3)
00251 #define CAN1_TDB3       ((*(REG32 (0xE004405C))))       //Transmit data bytes 5-8 (3)
00252 
00253 #define CAN2_MOD        ((*(REG32 (0xE0048000))))       //Control and operating mode of the CAN Controller
00254 #define CAN2_CMR        ((*(REG32 (0xE0048004))))       //Command bits that affect the state of CAN Controller
00255 #define CAN2_GSR        ((*(REG32 (0xE0048008))))       //Global Controller Status and Error Counters
00256 #define CAN2_ICR        ((*(REG32 (0xE004800C))))       //Interrupt status, Arbitration Lost Capture, Error Code Capture
00257 #define CAN2_IER        ((*(REG32 (0xE0048010))))       //Interrupt Enable
00258 #define CAN2_BTR        ((*(REG32 (0xE0048014))))       //Bus Timing
00259 #define CAN2_EWL        ((*(REG32 (0xE0048018))))       //Error Warning Limit
00260 #define CAN2_SR         ((*(REG32 (0xE004801C))))       //Status Register
00261 #define CAN2_RFS        ((*(REG32 (0xE0048020))))       //Receive frame status
00262 #define CAN2_RID        ((*(REG32 (0xE0048024))))       //Received Identifier
00263 #define CAN2_RDA        ((*(REG32 (0xE0048028))))       //Received data bytes 1-4
00264 #define CAN2_RDB        ((*(REG32 (0xE004802C))))       //Received data bytes 5-8
00265 #define CAN2_TFI1       ((*(REG32 (0xE0048030))))       //Transmit frame info (1)
00266 #define CAN2_TID1       ((*(REG32 (0xE0048034))))       //Transmit identifier (1)
00267 #define CAN2_TDA1       ((*(REG32 (0xE0048038))))       //Transmit data bytes 1-4 (1)
00268 #define CAN2_TDB1       ((*(REG32 (0xE004803C))))       //Transmit data bytes 5-8 (1)
00269 #define CAN2_TFI2       ((*(REG32 (0xE0048040))))       //Transmit Frame info (2)
00270 #define CAN2_TID2       ((*(REG32 (0xE0048044))))       //Transmit identifier (2)
00271 #define CAN2_TDA2       ((*(REG32 (0xE0048048))))       //Transmit data bytes 1-4 (2)
00272 #define CAN2_TDB2       ((*(REG32 (0xE004804C))))       //Transmit data bytes 5-8 (2)
00273 #define CAN2_TFI3       ((*(REG32 (0xE0048050))))       //Transmit frame info (3)
00274 #define CAN2_TID3       ((*(REG32 (0xE0048054))))       //Transmit identifier (3)
00275 #define CAN2_TDA3       ((*(REG32 (0xE0048058))))       //Transmit data bytes 1-4 (3)
00276 #define CAN2_TDB3       ((*(REG32 (0xE004805C))))       //Transmit data bytes 5-8 (3)
00277 
00278 #define CAN4_MOD        ((*(REG32 (0xE0050000))))       //Control and operating mode of the CAN Controller
00279 #define CAN4_CMR        ((*(REG32 (0xE0050004))))       //Command bits that affect the state of CAN Controller
00280 #define CAN4_GSR        ((*(REG32 (0xE0050008))))       //Global Controller Status and Error Counters
00281 #define CAN4_ICR        ((*(REG32 (0xE005000C))))       //Interrupt status, Arbitration Lost Capture, Error Code Capture
00282 #define CAN4_IER        ((*(REG32 (0xE0050010))))       //Interrupt Enable
00283 #define CAN4_BTR        ((*(REG32 (0xE0050014))))       //Bus Timing
00284 #define CAN4_EWL        ((*(REG32 (0xE0050018))))       //Error Warning Limit
00285 #define CAN4_SR         ((*(REG32 (0xE005001C))))       //Status Register
00286 #define CAN4_RFS        ((*(REG32 (0xE0050020))))       //Receive frame status
00287 #define CAN4_RID        ((*(REG32 (0xE0050024))))       //Received Identifier
00288 #define CAN4_RDA        ((*(REG32 (0xE0050028))))       //Received data bytes 1-4
00289 #define CAN4_RDB        ((*(REG32 (0xE005002C))))       //Received data bytes 5-8
00290 #define CAN4_TFI1       ((*(REG32 (0xE0050030))))       //Transmit frame info (1)
00291 #define CAN4_TID1       ((*(REG32 (0xE0050034))))       //Transmit identifier (1)
00292 #define CAN4_TDA1       ((*(REG32 (0xE0050038))))       //Transmit data bytes 1-4 (1)
00293 #define CAN4_TDB1       ((*(REG32 (0xE005003C))))       //Transmit data bytes 5-8 (1)
00294 #define CAN4_TFI2       ((*(REG32 (0xE0050040))))       //Transmit Frame info (2)
00295 #define CAN4_TID2       ((*(REG32 (0xE0050044))))       //Transmit identifier (2)
00296 #define CAN4_TDA2       ((*(REG32 (0xE0050048))))       //Transmit data bytes 1-4 (2)
00297 #define CAN4_TDB2       ((*(REG32 (0xE005004C))))       //Transmit data bytes 5-8 (2)
00298 #define CAN4_TFI3       ((*(REG32 (0xE0050050))))       //Transmit frame info (3)
00299 #define CAN4_TID3       ((*(REG32 (0xE0050054))))       //Transmit identifier (3)
00300 #define CAN4_TDA3       ((*(REG32 (0xE0050058))))       //Transmit data bytes 1-4 (3)
00301 #define CAN4_TDB3       ((*(REG32 (0xE005005C))))       //Transmit data bytes 5-8 (3)
00302 
00303 /*##############################################################################
00304 ## Timer 0 and Timer 1
00305 ##############################################################################*/
00306 
00307 /* ---- Timer 0 -------------------------------------------- */
00308 #define T0_IR           (*(REG32 (0xE0004000)))
00309 #define T0_TCR          (*(REG32 (0xE0004004)))
00310 #define T0_TC           (*(REG32 (0xE0004008)))
00311 #define T0_PR           (*(REG32 (0xE000400C)))
00312 #define T0_PC           (*(REG32 (0xE0004010)))
00313 #define T0_MCR          (*(REG32 (0xE0004014)))
00314 #define T0_MR0          (*(REG32 (0xE0004018)))
00315 #define T0_MR1          (*(REG32 (0xE000401C)))
00316 #define T0_MR2          (*(REG32 (0xE0004020)))
00317 #define T0_MR3          (*(REG32 (0xE0004024)))
00318 #define T0_CCR          (*(REG32 (0xE0004028)))
00319 #define T0_CR0          (*(REG32 (0xE000402C)))
00320 #define T0_CR1          (*(REG32 (0xE0004030)))
00321 #define T0_CR2          (*(REG32 (0xE0004034)))
00322 #define T0_CR3          (*(REG32 (0xE0004038)))
00323 #define T0_EMR          (*(REG32 (0xE000403C)))
00324 
00325 /* ---- Timer 1 -------------------------------------------- */
00326 #define T1_IR           (*(REG32 (0xE0008000)))
00327 #define T1_TCR          (*(REG32 (0xE0008004)))
00328 #define T1_TC           (*(REG32 (0xE0008008)))
00329 #define T1_PR           (*(REG32 (0xE000800C)))
00330 #define T1_PC           (*(REG32 (0xE0008010)))
00331 #define T1_MCR          (*(REG32 (0xE0008014)))
00332 #define T1_MR0          (*(REG32 (0xE0008018)))
00333 #define T1_MR1          (*(REG32 (0xE000801C)))
00334 #define T1_MR2          (*(REG32 (0xE0008020)))
00335 #define T1_MR3          (*(REG32 (0xE0008024)))
00336 #define T1_CCR          (*(REG32 (0xE0008028)))
00337 #define T1_CR0          (*(REG32 (0xE000802C)))
00338 #define T1_CR1          (*(REG32 (0xE0008030)))
00339 #define T1_CR2          (*(REG32 (0xE0008034)))
00340 #define T1_CR3          (*(REG32 (0xE0008038)))
00341 #define T1_EMR          (*(REG32 (0xE000803C)))
00342 
00343 
00344 /*##############################################################################
00345 ## PWM
00346 ##############################################################################*/
00347 
00348 #define PWM_IR          (*(REG32 (0xE0014000)))
00349 #define PWM_TCR         (*(REG32 (0xE0014004)))
00350 #define PWM_TC          (*(REG32 (0xE0014008)))
00351 #define PWM_PR          (*(REG32 (0xE001400C)))
00352 #define PWM_PC          (*(REG32 (0xE0014010)))
00353 #define PWM_MCR         (*(REG32 (0xE0014014)))
00354 #define PWM_MR0         (*(REG32 (0xE0014018)))
00355 #define PWM_MR1         (*(REG32 (0xE001401C)))
00356 #define PWM_MR2         (*(REG32 (0xE0014020)))
00357 #define PWM_MR3         (*(REG32 (0xE0014024)))
00358 #define PWM_MR4         (*(REG32 (0xE0014040)))
00359 #define PWM_MR5         (*(REG32 (0xE0014044)))
00360 #define PWM_MR6         (*(REG32 (0xE0014048)))
00361 #define PWM_EMR         (*(REG32 (0xE001403C)))
00362 #define PWM_PCR         (*(REG32 (0xE001404C)))
00363 #define PWM_LER         (*(REG32 (0xE0014050)))
00364 #define PWM_CCR         (*(REG32 (0xE0014028)))
00365 #define PWM_CR0         (*(REG32 (0xE001402C)))
00366 #define PWM_CR1         (*(REG32 (0xE0014030)))
00367 #define PWM_CR2         (*(REG32 (0xE0014034)))
00368 #define PWM_CR3         (*(REG32 (0xE0014038)))
00369 
00370 /*##############################################################################
00371 ## RTC
00372 ##############################################################################*/
00373 
00374 /* ---- RTC: Miscellaneous Register Group ------------------ */
00375 #define RTC_ILR         (*(REG32 (0xE0024000)))
00376 #define RTC_CTC         (*(REG32 (0xE0024004)))
00377 #define RTC_CCR         (*(REG32 (0xE0024008)))  
00378 #define RTC_CIIR        (*(REG32 (0xE002400C)))
00379 #define RTC_AMR         (*(REG32 (0xE0024010)))
00380 #define RTC_CTIME0      (*(REG32 (0xE0024014)))
00381 #define RTC_CTIME1      (*(REG32 (0xE0024018)))
00382 #define RTC_CTIME2      (*(REG32 (0xE002401C)))
00383 
00384 /* ---- RTC: Timer Control Group --------------------------- */
00385 #define RTC_SEC         (*(REG32 (0xE0024020)))
00386 #define RTC_MIN         (*(REG32 (0xE0024024)))
00387 #define RTC_HOUR        (*(REG32 (0xE0024028)))
00388 #define RTC_DOM         (*(REG32 (0xE002402C)))
00389 #define RTC_DOW         (*(REG32 (0xE0024030)))
00390 #define RTC_DOY         (*(REG32 (0xE0024034)))
00391 #define RTC_MONTH       (*(REG32 (0xE0024038)))
00392 #define RTC_YEAR        (*(REG32 (0xE002403C)))
00393 
00394 /* ---- RTC: Alarm Control Group --------------------------- */
00395 #define RTC_ALSEC       (*(REG32 (0xE0024060)))
00396 #define RTC_ALMIN       (*(REG32 (0xE0024064)))
00397 #define RTC_ALHOUR      (*(REG32 (0xE0024068)))
00398 #define RTC_ALDOM       (*(REG32 (0xE002406C)))
00399 #define RTC_ALDOW       (*(REG32 (0xE0024070)))
00400 #define RTC_ALDOY       (*(REG32 (0xE0024074)))
00401 #define RTC_ALMON       (*(REG32 (0xE0024078)))
00402 #define RTC_ALYEAR      (*(REG32 (0xE002407C)))
00403 
00404 /* ---- RTC: Reference Clock Divider Group ----------------- */
00405 #define RTC_PREINT      (*(REG32 (0xE0024080)))
00406 #define RTC_PREFRAC     (*(REG32 (0xE0024084)))
00407 
00408 
00409 /*##############################################################################
00410 ## AE - AD Converter
00411 ##############################################################################*/
00412 
00413 #define AD_ADCR        (*(REG32 (0xE0034000)))
00414 #define AD_ADDR        (*(REG32 (0xE0034004)))
00415 
00416 
00417 /*##############################################################################
00418 ## WD - Watchdog
00419 ##############################################################################*/
00420 
00421 #define WD_WDMOD        (*(REG32 (0xE0000000)))
00422 #define WD_WDTC         (*(REG32 (0xE0000004)))
00423 #define WD_WDFEED       (*(REG32 (0xE0000008)))
00424 #define WD_WDTV         (*(REG32 (0xE000000C)))
00425 
00426 
00427 /*##############################################################################
00428 ## SCB - System Control Block
00429 ##############################################################################*/
00430 
00431 #define SCB_EXTINT      (*(REG32 (0xE01FC140)))
00432 #define SCB_EXTWAKE     (*(REG32 (0xE01FC144)))
00433 #define SCB_EXTMODE     (*(REG32 (0xE01FC148)))
00434 #define SCB_EXTPOLAR    (*(REG32 (0xE01FC14C)))
00435 #define SCB_MEMMAP      (*(REG32 (0xE01FC040)))
00436 #define SCB_PLLCON      (*(REG32 (0xE01FC080)))
00437 #define SCB_PLLCFG      (*(REG32 (0xE01FC084)))
00438 #define SCB_PLLSTAT     (*(REG32 (0xE01FC088)))
00439 #define SCB_PLLFEED     (*(REG32 (0xE01FC08C)))
00440 #define SCB_PCON        (*(REG32 (0xE01FC0C0)))
00441 #define SCB_PCONP       (*(REG32 (0xE01FC0C4)))
00442 #define SCB_VPBDIV      (*(REG32 (0xE01FC100)))
00443 
00444 
00445 /*##############################################################################
00446 ## MAM - Memory Accelerator Module
00447 ##############################################################################*/
00448 
00449 #define MAM_MAMCR       (*(REG32 (0xE01FC000)))
00450 #define MAM_MAMTIM      (*(REG32 (0xE01FC004)))
00451 #define MAM_MAMMAP      (*(REG32 (0xE01FC040)))
00452 
00453 #define MAM_BCFG0       (*(REG32 (0xFFE00000)))
00454 #define MAM_BCFG1       (*(REG32 (0xFFE00004)))
00455 #define MAM_BCFG2       (*(REG32 (0xFFE00008)))
00456 #define MAM_BCFG3       (*(REG32 (0xFFE0000C)))
00457 
00458 #endif /* lpc2119_h */
00459