00001 /****************************************************************************** 00002 * 00003 * $RCSfile: $ 00004 * $Revision: $ 00005 * 00006 * Header file for Philips LPC ARM Processors. 00007 * Copyright 2004 R O SoftWare 00008 * 00009 * No guarantees, warrantees, or promises, implied or otherwise. 00010 * May be used for hobby or commercial purposes provided copyright 00011 * notice remains intact. 00012 * 00013 *****************************************************************************/ 00014 #ifndef INC_LPC_VIC_H 00015 #define INC_LPC_VIC_H 00016 00017 // Vectored Interrupt Controller Registers (VIC) 00018 typedef struct 00019 { 00020 REG32 irqStatus; // IRQ Status Register 00021 REG32 fiqStatus; // FIQ Status Register 00022 REG32 rawIntr; // Raw Interrupt Status Register 00023 REG32 intSelect; // Interrupt Select Register 00024 REG32 intEnable; // Interrupt Enable Register 00025 REG32 intEnClear; // Interrupt Enable Clear Register 00026 REG32 softInt; // Software Interrupt Register 00027 REG32 softIntClear; // Software Interrupt Clear Register 00028 REG32 protection; // Protection Enable Register 00029 REG32 _pad0[3]; 00030 REG32 vectAddr; // Vector Address Register 00031 REG32 defVectAddr; // Default Vector Address Register 00032 REG32 _pad1[50]; 00033 00034 union 00035 { 00036 struct 00037 { 00038 REG32 vectAddr0; // Vector Address 0 Register 00039 REG32 vectAddr1; // Vector Address 1 Register 00040 REG32 vectAddr2; // Vector Address 2 Register 00041 REG32 vectAddr3; // Vector Address 3 Register 00042 REG32 vectAddr4; // Vector Address 4 Register 00043 REG32 vectAddr5; // Vector Address 5 Register 00044 REG32 vectAddr6; // Vector Address 6 Register 00045 REG32 vectAddr7; // Vector Address 7 Register 00046 REG32 vectAddr8; // Vector Address 8 Register 00047 REG32 vectAddr9; // Vector Address 9 Register 00048 REG32 vectAddr10; // Vector Address 10 Register 00049 REG32 vectAddr11; // Vector Address 11 Register 00050 REG32 vectAddr12; // Vector Address 12 Register 00051 REG32 vectAddr13; // Vector Address 13 Register 00052 REG32 vectAddr14; // Vector Address 14 Register 00053 REG32 vectAddr15; // Vector Address 15 Register 00054 }; 00055 00056 REG32 vectAdrArray[16]; // Vector Address Register Array 00057 }; 00058 00059 REG32 _pad2[48]; 00060 00061 union 00062 { 00063 struct 00064 { 00065 REG32 vectCntl0; // Vector Control 0 Register 00066 REG32 vectCntl1; // Vector Control 1 Register 00067 REG32 vectCntl2; // Vector Control 2 Register 00068 REG32 vectCntl3; // Vector Control 3 Register 00069 REG32 vectCntl4; // Vector Control 4 Register 00070 REG32 vectCntl5; // Vector Control 5 Register 00071 REG32 vectCntl6; // Vector Control 6 Register 00072 REG32 vectCntl7; // Vector Control 7 Register 00073 REG32 vectCntl8; // Vector Control 8 Register 00074 REG32 vectCntl9; // Vector Control 9 Register 00075 REG32 vectCntl10; // Vector Control 10 Register 00076 REG32 vectCntl11; // Vector Control 11 Register 00077 REG32 vectCntl12; // Vector Control 12 Register 00078 REG32 vectCntl13; // Vector Control 13 Register 00079 REG32 vectCntl14; // Vector Control 14 Register 00080 REG32 vectCntl15; // Vector Control 15 Register 00081 }; 00082 00083 REG32 vectCtlArray[16]; // Vector Control Register Array 00084 }; 00085 } vicRegs_t; 00086 00087 // VIC Channel Assignments 00088 #define VIC_WDT 0 00089 #define VIC_TIMER0 4 00090 #define VIC_TIMER1 5 00091 #define VIC_UART0 6 00092 #define VIC_UART1 7 00093 #define VIC_PWM 8 00094 #define VIC_PWM0 8 00095 #define VIC_I2C 9 00096 #define VIC_SPI 10 00097 #define VIC_SPI0 10 00098 #define VIC_SPI1 11 00099 #define VIC_PLL 12 00100 #define VIC_RTC 13 00101 #define VIC_EINT0 14 00102 #define VIC_EINT1 15 00103 #define VIC_EINT2 16 00104 #define VIC_EINT3 17 00105 #define VIC_ADC 18 00106 00107 // Vector Control Register bit definitions 00108 #define VIC_ENABLE (1 << 5) 00109 00110 // Convert Channel Number to Bit Value 00111 #define VIC_BIT(chan) (1 << (chan)) 00112 00113 #endif 00114
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