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Defines | |
| #define | TxD0 (1 << 0) |
| #define | RxD0 (1 << 1) |
| #define | SCL (1 << 2) |
| #define | SDA (1 << 3) |
| #define | SCK0 (1 << 4) |
| #define | MISO0 (1 << 5) |
| #define | MOSI0 (1 << 6) |
| #define | SSEL0 (1 << 7) |
| #define | TxD1 (1 << 8) |
| #define | RxD1 (1 << 9) |
| #define | RST1 (1 << 10) |
| #define | CTS1 (1 << 11) |
| #define | DSR1 (1 << 12) |
| #define | DTR1 (1 << 13) |
| #define | DCD1 (1 << 14) |
| #define | RI1 (1 << 15) |
| #define | EINT0 (1 << 16) |
| #define | CAP1_2 (1 << 17) |
| #define | CAP1_3 (1 << 18) |
| #define | MAT1_2 (1 << 19) |
| #define | MAT1_3 (1 << 20) |
| #define | PWM5 (1 << 21) |
| #define | TD3 (1 << 22) |
| #define | RD2 (1 << 23) |
| #define | TD2 (1 << 24) |
| #define | RD1 (1 << 25) |
| #define | AIN0 (1 << 27) |
| #define | AIN1 (1 << 28) |
| #define | AIN2 (1 << 29) |
| #define | AIN3 (1 << 30) |
| #define | PWM1 TxD0 |
| #define | PWM3 RxD0 |
| #define | _EINT0 RxD0 |
| #define | CA1_0 SCL |
| #define | MAT0_0 SDA |
| #define | EINT1 SDA |
| #define | CA1_1 SCK0 |
| #define | MAT0_1 MISO0 |
| #define | CA1_2 MOSI0 |
| #define | PWM2 SSEL0 |
| #define | EINT2 SSEL0 |
| #define | PWM4 TxD1 |
| #define | PWM6 RxD1 |
| #define | EINT3 RxD1 |
| #define | CAP1_0 RTS1 |
| #define | CAP1_1 CTS1 |
| #define | MAT1_0 DSR1 |
| #define | RD4 DSR1 |
| #define | MAT1_1 DTR1 |
| #define | TD4 DTR1 |
| #define | _EINT1 DCD1 |
| #define | _EINT2 RI1 |
| #define | MAT_2 EINT0 |
| #define | _CA1_2 EINT0 |
| #define | SCK1 CAP1_2 |
| #define | _MAT1_2 CAP1_2 |
| #define | MISO1 CAP1_3 |
| #define | _MAT1_3 CAP1_3 |
| #define | MOSI1 MAT1_2 |
| #define | _CAP1_2 MAT1_2 |
| #define | SSEL1 MAT1_3 |
| #define | _EINT3 MAT1_3 |
| #define | RD3 PWM5 |
| #define | _CAP1_3 PWM5 |
| #define | _CA1_0 TD3 |
| #define | _MAT0_0 TD3 |
| #define | _CA1_1 AIN0 |
| #define | _MAT0_1 AIN0 |
| #define | __CA1_2 AIN1 |
| #define | MAT0_2 AIN1 |
| #define | CA1_3 AIN2 |
| #define | MAT0_3 AIN2 |
| #define | __EINT3 AIN3 |
| #define | __CA1_0 AIN3 |
| #define | CS0 (1 << 0) |
| #define | OE (1 << 1) |
| #define | TRACEPKT0 (1 << 16) |
| #define | TRACEPKT1 (1 << 17) |
| #define | TRACEPKT2 (1 << 18) |
| #define | TRACEPKT3 (1 << 19) |
| #define | TRACESYNC (1 << 20) |
| #define | PIPESTAT0 (1 << 21) |
| #define | PIPESTAT1 (1 << 22) |
| #define | PIPESTAT2 (1 << 23) |
| #define | TRACECLK (1 << 24) |
| #define | EXTIN0 (1 << 25) |
| #define | RTCK (1 << 26) |
| #define | TDO (1 << 27) |
| #define | TDI (1 << 28) |
| #define | TCK (1 << 29) |
| #define | TMS (1 << 30) |
| #define | TRST (1 << 31) |
| #define | D0 (1 << 0) |
| #define | D1 (1 << 1) |
| #define | D2 (1 << 2) |
| #define | D3 (1 << 3) |
| #define | D4 (1 << 4) |
| #define | D5 (1 << 5) |
| #define | D6 (1 << 6) |
| #define | D7 (1 << 7) |
| #define | D8 (1 << 8) |
| #define | D9 (1 << 9) |
| #define | D10 (1 << 10) |
| #define | D11 (1 << 11) |
| #define | D12 (1 << 12) |
| #define | D13 (1 << 13) |
| #define | D14 (1 << 14) |
| #define | D15 (1 << 15) |
| #define | D16 (1 << 16) |
| #define | D17 (1 << 17) |
| #define | D18 (1 << 18) |
| #define | D19 (1 << 19) |
| #define | D20 (1 << 20) |
| #define | D21 (1 << 21) |
| #define | D22 (1 << 22) |
| #define | D23 (1 << 23) |
| #define | D24 (1 << 24) |
| #define | D25 (1 << 25) |
| #define | D26 (1 << 26) |
| #define | D27 (1 << 27) |
| #define | D28 (1 << 28) |
| #define | D29 (1 << 29) |
| #define | D30 (1 << 30) |
| #define | D31 (1 << 31) |
| #define | BOOT0 D26 |
| #define | BOOT1 D27 |
| #define | AIN4 D30 |
| #define | AIN5 D31 |
1.4.7