projekty/Source/example1/src/Directive.h

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/*
 * $Id: directive.h,v 1.00 2007/09/11 15:45:00 BorisK Exp $
 *
 * Copyright (C) 2005 ONTRACK s.r.o.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA    
 * 02111-1307, USA.
 *
 * [1] ARM-based Microcontroller LPC2119/2129/2194/2292/9994, "Preliminary User Manual", February 03, 2004, Philips
 * Written by Boris Kralik <kralikbo@yahoo.com>, 2007
 *
 */
#ifndef DIRECTIVE_H
#define DIRECTIVE_H

//TIMER
#define TMR_IMR0        0
#define TMR_RMR0        1
#define TMR_SMR0        2
#define TMR_IMR1        3
#define TMR_RMR1        4
#define TMR_SMR1        5
#define TMR_IMR2        6
#define TMR_RMR2        7
#define TMR_SMR2        8
#define TMR_IMR3        9
#define TMR_RMR3        10
#define TMR_SMR3        11

#define TIR_MR0I        0            // Interrupt flag for match channel 0
#define TIR_MR1I        1            // Interrupt flag for match channel 1
#define TIR_MR2I        2            // Interrupt flag for match channel 2
#define TIR_MR3I        3            // Interrupt flag for match channel 3
#define TIR_CR0I        4            // Interrupt flag for capture channel 0 event
#define TIR_CR1I        5            // Interrupt flag for capture channel 1 event
#define TIR_CR2I        6            // Interrupt flag for capture channel 2 event
#define TIR_CR3I        7            // Interrupt flag for capture channel 3 event

// Timer Match Control Register Bit Definitions
#define TMCR_MR0_I      0
            // Enable Interrupt when MR0 matches TC
#define TMCR_MR0_R      1
            // Enable Reset of TC upon MR0 match
#define TMCR_MR0_S      2
            // Enable Stop of TC upon MR0 match
#define TMCR_MR1_I      3
            // Enable Interrupt when MR1 matches TC
#define TMCR_MR1_R      4
            // Enable Reset of TC upon MR1 match
#define TMCR_MR1_S      5
            // Enable Stop of TC upon MR1 match
#define TMCR_MR2_I      6
            // Enable Interrupt when MR2 matches TC
#define TMCR_MR2_R      7
            // Enable Reset of TC upon MR2 match
#define TMCR_MR2_S      8
            // Enable Stop of TC upon MR2 match
#define TMCR_MR3_I      9
            // Enable Interrupt when MR3 matches TC
#define TMCR_MR3_R      10
           // Enable Reset of TC upon MR3 match
#define TMCR_MR3_S      11
           // Enable Stop of TC upon MR3 match
#define TCR_CE          0
#define TCR_CR          1

//PCONP
#define PCC_PCTIM0      1
#define PCC_PCTIM1      2
#define PCC_PCURT0      3
#define PCC_PCURT1      4
#define PCC_PWM0        5
//   x
#define PCC_I2C         7
#define PCC_PCSPI0      8
#define PCC_RTC         9
#define PCC_PCSPI1      10
//   x
#define PCC_PCCAD       12
#define PCC_CAN1        13
#define PCC_CAN2        14
#define PCC_CAN3        15
#define PCC_CAN4        16

//PLLSTAT
#define PLLE    8
#define PLLC    9
#define PLOCK   10
//CAN.TxSR
#define TxSR_TS1        0       
#define TxSR_TS2        1
#define TxSR_TS3        2
#define TxSR_TS4        3

#define TxSR_TBS        0xF00
#define TxSR_TBS1       8
#define TxSR_TBS2       9
#define TxSR_TBS3       10
#define TxSR_TBS4       11

#define TxSR_TCS        0xF0000
#define TxSR_TCS1       16
#define TxSR_TCS2       17
#define TxSR_TCS3       18
#define TxSR_TCS4       19

//CAM.CMR
#define CMR_TR          0
#define CMR_AT          1
#define CMR_RRB         2
#define CMR_CDO         3
#define CMR_SRR         4
#define CMR_STB1        5
#define CMR_STB2        6
#define CMR_STB3        7
//CAN.RFS
#define BP      10
#define RTR     30
#define FF      31
//CAN.ICR
#define ICR_RI  0
#define ICR_TI1 1
#define ICR_EI  2
#define ICR_DOI 3
#define ICR_WUI 4
#define ICR_EPI 5
#define ICR_ALI 6
#define ICR_BEI 7
#define ICR_IDI 8
#define ICR_TI2 9
#define ICR_TI3 10
#define ICR_ERRDIR      21
//CAN.MOD
#define RM      0
#define LOM     1
#define STM     2
#define TPM     3
#define SM      4
#define RPM     5
#define TM      7
//CAN.RS
#define RS_RSB  0
#define RS_DOS  1
#define RS_TBS1 2
#define RS_TCS1 3
#define RS_RS   4
#define RS_TS1  5
#define RS_ES   6
#define RS_BS   7
//CAN.SR
#define SR_RBS  0
#define SR_DOS  1
#define SR_TBS1 2
#define SR_TBS2 10
#define SR_TBS3 18
#define SR_TCS1 3
#define SR_TCS2 11
#define SR_TCS3 19
#define SR_RS   4
#define SR_TS1  5
#define SR_TS2  13
#define SR_TS3  21
#define SR_ES   6
#define SR_BS   7
        
//CAN.GSR
#define GSR_RBS 0
#define GSR_DOS 1
#define GSR_TBS 2
#define GSR_TCS 3
#define GSR_RS  4
#define GSR_TS  5
#define GSR_ES  6
#define GSR_BS  7

//CAN.TFI1
#define TFI1_PRIO       0
//#define       TFI1_DLC        (8 << 16)
#define TFI1_RTR        30
#define TFI1_FF         (1 << 31)

//CAN.IER
#define RIE     0
#define TIE1    1
#define EIE     2
#define DOIE    3
#define WUIE    4
#define EPIE    5
#define ALIE    6
#define BEIE    7
#define IDIE    8
#define TIE2    9
#define TIE3    10

//Acctptance filter

//CAN Disable bit in Acceptance filter
#define CAN_DISABLE     12
#define ACC_VPB_BASE    0xE0038000

#define ACCFILTER_STD   (ACC_VPB_BASE   +       0x00000000)
//StandardFilter places reservated for eight 32bit words
#define ACCFILTER_GRP   (ACCFILTER_STD  +       0x00000000)
//GroupFilter places reservated for three 32bit words
#define ACCFILTER_IND   (ACCFILTER_GRP  +       0x00000000)
//IndividualFilter places reservated for three 32bit words
#define ACCFILTER_EFG   (ACCFILTER_IND  +       0x00000000)

#define ACCFILTER_OFF   0
#define ACCFILTER_BP    1
#define ACCFILTER_EFCAN 2
#define TPM     3




#endif

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