projekty/Source/example1/src/CanTest.c

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/*
 * $Id: CanTest.h,v 1.00 2007/09/11 15:45:00 BorisK Exp $
 *
 * Copyright (C) 2005 ONTRACK s.r.o.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA    
 * 02111-1307, USA.
 *
 * [1] ARM-based Microcontroller LPC2119/2129/2194/2292/9994, "Preliminary User Manual", February 03, 2004, Philips
 * Written by Boris Kralik <kralikbo@yahoo.com>, 2007
 *
 */
#ifndef CANTEST_C
#define CANTEST_C
#include "CanTest.h"

/******************** TestTxSR **********************************
        Description     Test CAN_T
        Name            TIMER0_Int
        @param          str
        @param          sCANxEnable
        @return         void
*********************************************************/
void TestTxSR(char *str,short sCANxEnable) {
        short error=0;
        disableIRQ();WD_Reset();
        if ((CAN_TxSR   & (1 << TxSR_TS1))&(sCANxEnable &= 0x1)){printf("\n\r\t%s:CAN1 is sending message (TxSR=0x%X)",str,CAN_TxSR);enableIRQ();WD_Reset();error=1;}else WD_Reset();
        if ((CAN_TxSR   & (1 << TxSR_TS2))&(sCANxEnable &= 0x2)){printf("\n\r\t%s:CAN2 is sending message (TxSR=0x%X)",str,CAN_TxSR);enableIRQ();WD_Reset();error=1;}else WD_Reset();
        if ((CAN_TxSR   & (1 << TxSR_TS4))&(sCANxEnable &= 0x4)){printf("\n\r\t%s:CAN4 is sending message (TxSR=0x%X)",str,CAN_TxSR);enableIRQ();WD_Reset();error=1;}else WD_Reset();
        if (!(CAN_TxSR& TxSR_TCS)){printf("\n\r\tCAN_TxSR.TCS=0x%X (TxSR=0x%X)",((CAN_TxSR & 0x00F0000) >> 16),CAN_TxSR);enableIRQ();WD_Reset();error=1;}else WD_Reset();
        if (!(CAN_TxSR& 0xF00)){printf("\n\r\t%s:All 3Tx buffers is not avaiable.(TxSR=0x%X)",str,CAN_TxSR);enableIRQ();WD_Reset();error=1;}else WD_Reset();
        if (!(CAN_TxSR& 0x0F)) {printf("\n\r\t%s:Not successfully (TxSR=0x%X)",str,CAN_TxSR);enableIRQ();WD_Reset();error=1;}else WD_Reset();
        //WD_Reset();if (error == 0) printf("\n\r\t%s:No error in TxSR. [0x%X]",str,CAN_TxSR); WD_Reset();
}
uint32_t TestICR(short sCAN,char *str,short enable){
        short error=0;
        //printf("\n\r****** TestICR CAN%d_ICR %s ******",sCAN,str);WD_Reset();
        uint32_t        icr=0;
        uint8_t ERRBIT=0;
        switch(sCAN)
        {
                case 1:icr= CAN1_ICR;break;
                case 2:icr= CAN2_ICR;break;
                case 4:icr= CAN4_ICR;break;
        }
        WD_Reset();if (icr & (1 << ICR_RI) ){printf("\n\r\t%s:Receive interrupt (RI) !",str);           WD_Reset();error=1;}
        WD_Reset();if (icr & (1 << ICR_TI1)){printf("\n\r\t%s:Receive Transmit1 (TI1) interrupt !",str);WD_Reset();error=1;}
        WD_Reset();if (icr & (1 << ICR_EI) ){printf("\n\r\t%s:ErrorWarning (EI) interrupt !(CAN%d.SR=0x%X)",str,sCAN,CAN1_SR);  WD_Reset();error=1;}
        WD_Reset();if (icr & (1 << ICR_DOI)){printf("\n\r\t%s:DataOverrun (DOI) interrupt !",str);      WD_Reset();error=1;}
        WD_Reset();if (icr & (1 << ICR_WUI)){printf("\n\r\t%s:Wake-up (WUI) interrupt !",str);          WD_Reset();error=1;}
        WD_Reset();if (icr & (1 << ICR_EPI)){printf("\n\r\t%s:Error passive (EPI) interrupt !",str);    WD_Reset();error=1;}
        WD_Reset();if (icr & (1 << ICR_ALI)){printf("\n\r\t%s:Arbitration lost (ALI) interrupt !",str);WD_Reset();error=1;}
        WD_Reset();if (icr & (1 << ICR_BEI)){printf("\n\r\t%s:Bus Error (BEI) interrupt !",str);WD_Reset();error=1;}
        ERRBIT = ((icr & 0x1F0000) >> 16);
        switch(ERRBIT)
        {
                case 0x0: WD_Reset();break;
                case 0x2: printf("\n\r\t%s:Error in ID28:21. [0x%x]",str,ERRBIT);WD_Reset();error=1;break;
                case 0x3: printf("\n\r\t%s:Error in Error 'Start of frame. [0x%x]",str,ERRBIT);WD_Reset();error=1;break;
                case 0x4: printf("\n\r\t%s:Error in Error 'SRTR bit. [0x%x]",str,ERRBIT);WD_Reset();error=1;break;
                case 0x5: printf("\n\r\t%s:Error in IDE bit. [0x%x]",str,ERRBIT);WD_Reset();error=1;break;
                case 0x6: printf("\n\r\t%s:Error in ID20:18. [0x%x]",str,ERRBIT);WD_Reset();error=1;break;
                case 0x7: printf("\n\r\t%s:Error in ID17:13. [0x%x]",str,ERRBIT);WD_Reset();error=1;break;
                case 0x8: printf("\n\r\t%s:Error in CRC. [0x%x]",str,ERRBIT);WD_Reset();error=1;break;
                case 0xA: printf("\n\r\t%s:Error in Data field. [0x%X]",str,ERRBIT);WD_Reset();error=1;break;
                case 0xB: printf("\n\r\t%s:Error in DLC. [0x%x]",str,ERRBIT);WD_Reset();error=1;break;
                case 0xC: printf("\n\r\t%s:Error in RTR bit. [0x%x]",str,ERRBIT);WD_Reset();error=1;break;
                case 0xE: printf("\n\r\t%s:Error in ID4:0. [0x%x]",str,ERRBIT);WD_Reset();error=1;break;
                case 0xF: printf("\n\r\t%s:Error in ID12:5. [0x%x]",str,ERRBIT);WD_Reset();error=1;break;
                case 0x11:printf("\n\r\t%s:Error in Active error flag. [0x%x]",str,ERRBIT);WD_Reset();error=1;break;
                case 0x12:printf("\n\r\t%s:Error in Intermission. [0x%x]",str,ERRBIT);WD_Reset();error=1;break;
                case 0x13:printf("\n\r\t%s:Error in Dominant OK bits. [0x%x]",str,ERRBIT);WD_Reset();error=1;break;
                case 0x16:printf("\n\r\t%s:Error in Passive error flag. [0x%x]",str,ERRBIT);WD_Reset();error=1;break;
                case 0x18:printf("\n\r\t%s:Error in CRC Delimiter. [0x%X]",str,ERRBIT);WD_Reset();error=1;break;
                case 0x19:printf("\n\r\t%s:Error in ACK slot. [ERRBIT:0x%x]",str,ERRBIT);WD_Reset();error=1;break;
                case 0x1A:printf("\n\r\t%s:Error in End of Frame. [0x%X]",str,ERRBIT);WD_Reset();error=1;break;
                case 0x1B:printf("\n\r\t%s:Error in Ack delimiter. [0x%X]",str,ERRBIT);WD_Reset();error=1;break;
                case 0x1C:printf("\n\r\t%s:Error in Overload flag. [0x%X]",str,ERRBIT);WD_Reset();error=1;break;
                default:printf("\n\r\t%s:str,ICR Error. [0x%X]",str,ERRBIT);WD_Reset();error=1;break;
        }
        WD_Reset();if (error == 0) printf("\n\r\t%s:No error in CAN%d_ICR.",str,sCAN);else {printf("\n\r\t%s:CAN%d_ICR=0x%X",str,sCAN,icr);}
        return icr;
}
short    TestRFS(short sCan,char *str,short sCANxEnable) {
        disableIRQ();
        uint32_t        rfs=CAN1_RFS;
        uint32_t error = 0;
        switch(sCan)
        {
                case 1:if (sCANxEnable &= 0x1) {rfs=CAN1_RFS;break;} else return 1;
                case 2:if (sCANxEnable &= 0x2) {rfs=CAN2_RFS;break;} else return 1;
                case 4:if (sCANxEnable &= 0x4) {rfs=CAN4_RFS;break;} else return 1;
        }
        if (rfs &       (1 << BP))      {printf("\n\r\tCurrent message was received on CAN%d in AF Bypass mode.",sCan);}
        if (error == 0) printf("\n\r\t%s:No error in RFS",str);
        printf(" ID:Index=0x%X DLC=0x%X BP:0x%X rfs:0x%X",      (rfs & 0x3FF),((rfs & 0xF0000)>>16),((rfs & 0x400) >> 10),rfs);
        return 0;
}
short    TestSR(short sCan,char *str,short sCANxEnable) {
        uint32_t        sr=CAN1_SR,pcconp=SCB_PCONP;
        short error=0;
        disableIRQ();
        switch(sCan){
                case 1:sr=CAN1_SR;if ((pcconp & (1 << PCC_CAN1)) == 0) {printf("\n\r\t!!! CAN1 is off.[SCB_PCONP=0x%X,0x%X ]",SCB_PCONP,(pcconp & (1 << PCC_CAN1)));enableIRQ();WD_Reset();return 1;}break;
                case 2:sr=CAN2_SR;if ((pcconp & (1 << PCC_CAN2)) == 0) {printf("\n\r\t!!! CAN2 is off.[SCB_PCONP=0x%X]",SCB_PCONP,(pcconp & (1 << PCC_CAN2)));enableIRQ();WD_Reset();return 1;}break;
                case 4:sr=CAN4_SR;if ((pcconp & (1 << PCC_CAN4)) == 0) {printf("\n\r\t!!! CAN4 is off.[SCB_PCONP=0x%X]",SCB_PCONP,(pcconp & (1 << PCC_CAN4)));enableIRQ();WD_Reset();return 1;}break;
        }
        //printf("\n\r\t\tPCCAN=0x%X",pcconp);
        WD_Reset();if ( (sr & (1 << RS_RSB)&(SCB_PCONP & pcconp))){printf("\n\r\t%s:Received message is applicable in CAN%dSR.RDA (SR=0x%X)",str,sCan,sr);error=1;}
        WD_Reset();if ( (sr & (1 << RS_DOS))&(SCB_PCONP & pcconp)){printf("\n\r\t%s:CAN%d_SR.DOS == 1 (SR=0x%X) !!!",str,sCan,sr);error=1;}
        WD_Reset();if (!(sr & (1 << RS_TBS1))&(SCB_PCONP & pcconp)){printf("\n\r\t%s:CAN%d_SR.TBS1 == 0 (SR=0x%X) !!!",str,sCan,sr);error=1;}
        WD_Reset();if (!(sr & (1 << RS_TCS1))&(SCB_PCONP & pcconp)){printf("\n\r\t%s:CAN%d_SR.Transmission 1 not been completed (SR=0x%X) !!!",str,sCan,sr);error=1;}
        WD_Reset();if ((sr & (1 << RS_RS)))   {printf("\n\r\t%s:CAN%d_SR.RS controller receiving message (SR=0x%X) !!!",str,sCan,sr);error=1;}
        WD_Reset();if ((sr & (1 << RS_TS1)))  {printf("\n\r\t%s:CAN%d_SR.TS1 controller trasmitting message (SR=0x%X) !!!",str,sCan,sr);error=1;}
        WD_Reset();if ((sr & (1 << RS_ES)))   {printf("\n\r\t%s:CAN%d_SR.ES (SR=0x%X) !!!",str,sCan,sr);error=1;}
        WD_Reset();if ((sr & (1 << RS_BS)))   {printf("\n\r\t%s:CAN%d_SR.BS (SR=0x%X) !!!",str,sCan,sr);error=1;}
        if (error == 0) printf("\n\r\t%s:No error in CAN%d_SR.",str,sCan);
        enableIRQ();WD_Reset();
        return error;
}
short    TestGSR(short sCan,char *str,short sCANxEnable){
        short error=0;
        disableIRQ();
        uint32_t        gsr=CAN1_GSR,tcs=0;
        switch(sCan)
        {
                case 1:gsr=CAN1_GSR;tcs=(CAN1_GSR & (1 << GSR_TCS));break;
                case 2:gsr=CAN2_GSR;tcs=(CAN2_GSR & (1 << GSR_TCS));break;
                case 4:gsr=CAN4_GSR;tcs=(CAN4_GSR & (1 << GSR_TCS));break;
        }
        WD_Reset();if ((gsr & (1 << GSR_DOS)) & tcs){printf("\n\r\t%s:Message on CAN%d was lost (GSR=0x%X)",str,sCan,gsr);                              error=1;}
        WD_Reset();if(!(gsr & (1 << GSR_TBS)) & tcs){printf("\n\r\t%s:Transfer on CAN%d is pending ! (GSR=0x%X)",str,sCan,gsr);                         error=1;}
        WD_Reset();if(!(gsr & (1 << GSR_TCS)) & tcs){printf("\n\r\t%s:Message on CAN%d not been successfully completed (GSR=0x%X)",str,sCan,gsr);       error=1;}
        WD_Reset();if ((gsr & (1 << GSR_TS)) & tcs) {printf("\n\r\t%s:TS:CAN%d is pending ! (GSR=0x%X)",str,sCan,gsr);                                  error=1;}
        WD_Reset();if ((gsr & (1 << GSR_ES)) & tcs) {printf("\n\r\t%s:Error status (GSR=0x%X)(RXERR=0x%X)(TXERR=0x%X)",str,gsr,((gsr & 0xFF0000) >> 16),((gsr & 0xFF000000) >> 24));error=1;}
        WD_Reset();if ((gsr & (1 << GSR_BS)) & tcs) {printf("\n\r\t%s:Bus CAN%d is OFF (GSR=0x%X)",str,sCan,gsr);                                       error=1;}
        if (error == 0) printf("\n\r\t%s:No error in CAN%d_GSR=0x%X.",str,sCan,gsr);
        enableIRQ();WD_Reset();
        return 0;
}
void     PrintCANsStatus(short can,char *str,short sCANxEnable){
        disableIRQ();
        printf("\n\r\t==== Status CAN%d (%s)====",can,str);
        TestSR(can,str,sCANxEnable);
        TestGSR(can,str,sCANxEnable);
        TestICR(can,str,sCANxEnable);
        TestTxSR(str,sCANxEnable);
        printf("\r\n\t==========================");
        WD_Reset();
        enableIRQ();
}

#endif

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