# Reading c:/Modeltech_xe/win32xoem/../tcl/vsim/pref.tcl 
# do tb_disvint.fdo 
# Model Technology ModelSim XE vcom 5.5e_p1 Compiler 2001.11 Nov 16 2001
# Model Technology ModelSim XE vcom 5.5e_p1 Compiler 2001.11 Nov 16 2001
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package p_adig
# -- Compiling package p_disdig
# -- Loading package textio
# -- Compiling package body p_disdig
# -- Loading package p_disdig
# WARNING[10]: C:/VHDL_Pack/P_DISDIG.VHD(39): Using 1076-1987 syntax for file declaration.
# Model Technology ModelSim XE vcom 5.5e_p1 Compiler 2001.11 Nov 16 2001
# Model Technology ModelSim XE vcom 5.5e_p1 Compiler 2001.11 Nov 16 2001
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling package p_adig
# Model Technology ModelSim XE vcom 5.5e_p1 Compiler 2001.11 Nov 16 2001
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package p_adig
# -- Compiling entity disvint
# Model Technology ModelSim XE vcom 5.5e_p1 Compiler 2001.11 Nov 16 2001
# -- Loading package standard
# -- Compiling architecture behavioral of disvint
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package p_adig
# -- Loading entity disvint
# Model Technology ModelSim XE vcom 5.5e_p1 Compiler 2001.11 Nov 16 2001
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package p_adig
# -- Loading package p_disdig
# -- Compiling entity testbench
# Model Technology ModelSim XE vcom 5.5e_p1 Compiler 2001.11 Nov 16 2001
# -- Loading package standard
# -- Compiling architecture behavior of testbench
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package p_adig
# -- Loading package p_disdig
# -- Loading entity testbench
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading entity disvint
# vsim -lib work -t 1ps -L xilinxcorelib testbench 
# Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.# Loading c:/Modeltech_xe/win32xoem/../std.standard
# Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body)
# Loading c:/Modeltech_xe/win32xoem/../ieee.numeric_std(body)
# Loading work.p_adig
# Loading c:/Modeltech_xe/win32xoem/../std.textio(body)
# Loading work.p_disdig(body)
# Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body)
# Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body)
# Loading work.testbench(behavior)
# Loading work.disvint(behavioral)
# .wave
# .structure
# .signals
exit
