# Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 
# do tb_disvint.fdo 
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003
# Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling package p_adig
# Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003
# Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package p_adig
# -- Compiling package p_disdig
# -- Loading package textio
# -- Compiling package body p_disdig
# -- Loading package p_disdig
# WARNING[10]: c:/workshop/VHDL_Pack/P_DISDIG.VHD(38): Using 1076-1987 syntax for file declaration.
# Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package p_adig
# -- Compiling entity disvint
# Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003
# -- Loading package standard
# -- Compiling architecture behavioral of disvint
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package p_adig
# -- Loading entity disvint
# Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package p_adig
# -- Loading package p_disdig
# -- Compiling entity testbench
# Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003
# -- Loading package standard
# -- Compiling architecture behavior of testbench
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package p_adig
# -- Loading package p_disdig
# -- Loading entity testbench
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading entity disvint
# vsim -L xilinxcorelib -lib work -t 1ps testbench 
# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.numeric_std(body)
# Loading work.p_adig
# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
# Loading work.p_disdig(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body)
# Loading work.testbench(behavior)
# Loading work.disvint(behavioral)
# .wave
# .structure
# .signals
restart
run 90 ns
run 90 ns
exit
