m255
o
cModel Technology
dC:\LabVHDL_4
Eareg
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_arith XinSYO>L7_n;;dMn;72:52
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
w1040096698
Fareg.vhd
l0
L6
VYl<AkM`S38E[06@]IL:SH1
OX;C;5.5e_p1;15
31
o-just e -93 -explicit -O0
Abehavioral
DE work areg Yl<AkM`S38E[06@]IL:SH1
l16
L14
V;g5E6H?:GFgo464NBORKJ2
OX;C;5.5e_p1;15
31
M3 ieee std_logic_1164
M2 ieee std_logic_arith
M1 ieee std_logic_unsigned
o-skip e -93 -explicit -O0
Careg_cfg
DE work areg Yl<AkM`S38E[06@]IL:SH1
DA work testbench testbench_arch ]Z9i8`;RK^53XKiZWYI?a1
DP std textio K]Z^fghZ6B=BjnK5NomDT3
DP ieee std_logic_textio 8YS?iX`WD1REQG`ZRYQGB2
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_arith XinSYO>L7_n;;dMn;72:52
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work testbench LL=2H@hY@c0IQcKjXoSYM3
w1040097120
Fwtb_areg.vhw
l0
L0
Vg2ch:aRd4Dm=O>6Jg]>P@0
OX;C;5.5e_p1;15
31
M5 ieee std_logic_1164
M4 ieee std_logic_arith
M3 ieee std_logic_unsigned
M2 ieee std_logic_textio
M1 std textio
atestbench_arch
etestbench
o-skip e -93 -explicit -O0
Etestbench
DP ieee numeric_std JEAJIQRRkDSZF:PY1:8aa1
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
w1040097922
Ftb_areg.vhd
l0
L15
Vo2;IEQ6cK>El<C?DMU]SW1
OX;C;5.5e_p1;15
31
o-just e -93 -explicit -O0
Abehavior
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_arith XinSYO>L7_n;;dMn;72:52
DE work areg Yl<AkM`S38E[06@]IL:SH1
DE work testbench o2;IEQ6cK>El<C?DMU]SW1
l38
L18
Vh:?Z]BJIk7;djk`:`4=DG2
OX;C;5.5e_p1;15
31
M4 ieee std_logic_1164
M3 ieee numeric_std
M2 ieee std_logic_arith
M1 ieee std_logic_unsigned
o-skip e -93 -explicit -O0
Atestbench_arch
DE work areg Yl<AkM`S38E[06@]IL:SH1
DE work testbench LL=2H@hY@c0IQcKjXoSYM3
l46
L26
V]Z9i8`;RK^53XKiZWYI?a1
OX;C;5.5e_p1;15
31
M5 ieee std_logic_1164
M4 ieee std_logic_arith
M3 ieee std_logic_unsigned
M2 ieee std_logic_textio
M1 std textio
o-skip e -93 -explicit -O0
