# Reading c:/Modeltech_xe/win32xoem/../tcl/vsim/pref.tcl 
# do tb_areg.fdo 
# Model Technology ModelSim XE vcom 5.5e_p1 Compiler 2001.11 Nov 16 2001
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity areg
# Model Technology ModelSim XE vcom 5.5e_p1 Compiler 2001.11 Nov 16 2001
# -- Loading package standard
# -- Compiling architecture behavioral of areg
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading entity areg
# Model Technology ModelSim XE vcom 5.5e_p1 Compiler 2001.11 Nov 16 2001
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling entity testbench
# Model Technology ModelSim XE vcom 5.5e_p1 Compiler 2001.11 Nov 16 2001
# -- Loading package standard
# -- Compiling architecture behavior of testbench
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading entity testbench
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading entity areg
# WARNING[1]: tb_areg.vhd(46): Types do not match for port new_alarm_time
# WARNING[1]: tb_areg.vhd(46): A use of this default binding for this component instantiation will result in an elaboration error.
# WARNING[1]: tb_areg.vhd(46): Types do not match for port alarm_time
# WARNING[1]: tb_areg.vhd(46): A use of this default binding for this component instantiation will result in an elaboration error.
# ERROR: tb_areg.vhd(56): Type conflict in integer literal. Type std_logic_vector versus integer.
# ERROR: tb_areg.vhd(66): VHDL Compiler exiting
# ERROR: c:/Modeltech_xe/win32xoem/vcom failed.
# Error in macro ./tb_areg.fdo line 8
# c:/Modeltech_xe/win32xoem/vcom failed.
#     while executing
# "vcom -skip e -93 -explicit   tb_areg.vhd"
Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do tb_areg.fdo
# Model Technology ModelSim XE vcom 5.5e_p1 Compiler 2001.11 Nov 16 2001
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity areg
# Model Technology ModelSim XE vcom 5.5e_p1 Compiler 2001.11 Nov 16 2001
# -- Loading package standard
# -- Compiling architecture behavioral of areg
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading entity areg
# Model Technology ModelSim XE vcom 5.5e_p1 Compiler 2001.11 Nov 16 2001
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling entity testbench
# Model Technology ModelSim XE vcom 5.5e_p1 Compiler 2001.11 Nov 16 2001
# -- Loading package standard
# -- Compiling architecture behavior of testbench
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading entity testbench
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading entity areg
# vsim -lib work -t 1ps -L xilinxcorelib testbench 
# Loading c:/Modeltech_xe/win32xoem/../std.standard
# Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body)
# Loading c:/Modeltech_xe/win32xoem/../ieee.numeric_std(body)
# Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body)
# Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body)
# Loading work.testbench(behavior)
# Loading work.areg(behavioral)
# .wave
# .structure
# .signals
do tb_areg.fdo
# Model Technology ModelSim XE vcom 5.5e_p1 Compiler 2001.11 Nov 16 2001
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity areg
# Model Technology ModelSim XE vcom 5.5e_p1 Compiler 2001.11 Nov 16 2001
# -- Loading package standard
# -- Compiling architecture behavioral of areg
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading entity areg
# Model Technology ModelSim XE vcom 5.5e_p1 Compiler 2001.11 Nov 16 2001
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling entity testbench
# Model Technology ModelSim XE vcom 5.5e_p1 Compiler 2001.11 Nov 16 2001
# -- Loading package standard
# -- Compiling architecture behavior of testbench
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading entity testbench
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading entity areg
# vsim -lib work -t 1ps -L xilinxcorelib testbench 
# Loading c:/Modeltech_xe/win32xoem/../std.standard
# Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body)
# Loading c:/Modeltech_xe/win32xoem/../ieee.numeric_std(body)
# Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body)
# Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body)
# Loading work.testbench(behavior)
# Loading work.areg(behavioral)
# .wave
# .structure
# .signals
exit
