m255
o
cModel Technology
dC:\LabVHDL_3
Edisvbit
DP work p_adig PMVFQnamaV>WEcCN_n2mJ2
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_arith XinSYO>L7_n;;dMn;72:52
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
w1039769897
Fdisvbit.vhd
l0
L8
VjQ0=e@n1^IS]CzI[^4^l=2
OX;C;5.5e_p1;15
31
o-just e -93 -explicit -O0
Abehavioral
DE work disvbit jQ0=e@n1^IS]CzI[^4^l=2
l23
L19
VjLfo[0Y=_Y8bL?lih5:Li3
OX;C;5.5e_p1;15
31
M4 ieee std_logic_1164
M3 ieee std_logic_arith
M2 ieee std_logic_unsigned
M1 work p_adig
o-skip e -93 -explicit -O0
Pp_adig
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
w1039746723
FC:/VHDL_Pack/P_ADIG.VHD
l0
L6
VPMVFQnamaV>WEcCN_n2mJ2
OX;C;5.5e_p1;15
31
M1 ieee std_logic_1164
o-skip e -93 -explicit -work work -O0
Etestbench
DP work p_adig PMVFQnamaV>WEcCN_n2mJ2
DP ieee numeric_std JEAJIQRRkDSZF:PY1:8aa1
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
w1039769849
Ftb_disvbit.vhd
l0
L17
Vh;;3EQ:kJPoIn2W`GGHm@0
OX;C;5.5e_p1;15
31
o-just e -93 -explicit -O0
Abehavior
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_arith XinSYO>L7_n;;dMn;72:52
DE work disvbit jQ0=e@n1^IS]CzI[^4^l=2
DE work testbench h;;3EQ:kJPoIn2W`GGHm@0
l39
L20
V=5Sd`=6Deci1jm_MklEfz2
OX;C;5.5e_p1;15
31
M5 ieee std_logic_1164
M4 ieee numeric_std
M3 work p_adig
M2 ieee std_logic_arith
M1 ieee std_logic_unsigned
o-skip e -93 -explicit -O0
