# Reading c:/Modeltech_xe/win32xoem/../tcl/vsim/pref.tcl 
# do tb_disvbit.fdo 
# Model Technology ModelSim XE vcom 5.5e_p1 Compiler 2001.11 Nov 16 2001
# Model Technology ModelSim XE vcom 5.5e_p1 Compiler 2001.11 Nov 16 2001
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling package p_adig
# Model Technology ModelSim XE vcom 5.5e_p1 Compiler 2001.11 Nov 16 2001
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package p_adig
# -- Compiling entity disvbit
# Model Technology ModelSim XE vcom 5.5e_p1 Compiler 2001.11 Nov 16 2001
# -- Loading package standard
# -- Compiling architecture behavioral of disvbit
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package p_adig
# -- Loading entity disvbit
# Model Technology ModelSim XE vcom 5.5e_p1 Compiler 2001.11 Nov 16 2001
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package p_adig
# -- Compiling entity testbench
# Model Technology ModelSim XE vcom 5.5e_p1 Compiler 2001.11 Nov 16 2001
# -- Loading package standard
# -- Compiling architecture behavior of testbench
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package p_adig
# -- Loading entity testbench
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading entity disvbit
# vsim -lib work -t 1ps -L xilinxcorelib testbench 
# Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.# Loading c:/Modeltech_xe/win32xoem/../std.standard
# Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body)
# Loading c:/Modeltech_xe/win32xoem/../ieee.numeric_std(body)
# Loading work.p_adig
# Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body)
# Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body)
# Loading work.testbench(behavior)
# Loading work.disvbit(behavioral)
# .wave
# .structure
# .signals
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /testbench/uut
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /testbench/uut
exit
