# Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 
# do tb_disvbit.tdo 
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package vital_timing
# -- Compiling entity roc
# -- Compiling entity toc
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Loading package vital_primitives
# -- Loading package textio
# -- Loading package vpackage
# -- Compiling entity disvbit
# Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003
# -- Loading package standard
# -- Compiling architecture roc_v of roc
# -- Loading package std_logic_1164
# -- Loading package vital_timing
# -- Loading entity roc
# -- Compiling architecture toc_v of toc
# -- Loading entity toc
# -- Compiling architecture structure of disvbit
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Loading package vital_primitives
# -- Loading package textio
# -- Loading package vpackage
# -- Loading entity disvbit
# -- Loading entity x_buf
# -- Loading entity x_inv
# -- Loading entity x_tri
# -- Loading entity x_lut4
# -- Loading entity x_one
# -- Loading entity roc
# -- Loading entity toc
# Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package p_adig
# -- Compiling entity testbench
# Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003
# -- Loading package standard
# -- Compiling architecture behavior of testbench
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package p_adig
# -- Loading entity testbench
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Loading package vital_primitives
# -- Loading package textio
# -- Loading package vpackage
# -- Loading entity disvbit
# vsim -lib work -sdfmax /UUT=disvbit_timesim.sdf -t 1ps testbench 
# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.numeric_std(body)
# Loading work.p_adig
# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../vital2000.vital_timing(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/simprim.vcomponents
# Loading C:/Modeltech_xe_starter/win32xoem/../vital2000.vital_primitives(body)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/simprim.vpackage(body)
# Loading work.testbench(behavior)
# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_timing(body)
# Loading work.disvbit(structure)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/simprim.x_buf(x_buf_v)
# Loading disvbit_timesim.sdf
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/simprim.x_inv(x_inv_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/simprim.x_tri(x_tri_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/simprim.x_lut4(x_lut4_v)
# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/simprim.x_one(x_one_v)
# Loading work.roc(roc_v)
# Loading work.toc(toc_v)
# WARNING: Design size of 519 statements or 2 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Note: (vsim-3587) SDF Backannotation Successfully Completed.
#    Time: 0 ps  Iteration: 0  Region: /testbench  File: tb_disvbit.vhd
# .wave
# .structure
# .signals
view dataflow
# WARNING: No extended dataflow License exists
# .dataflow
destroy .signals
exit
