# Reading c:/Modeltech_xe/win32xoem/../tcl/vsim/pref.tcl 
# do tb_alarm_reg.fdo 
# Model Technology ModelSim XE vcom 5.5e_p1 Compiler 2001.11 Nov 16 2001
# Model Technology ModelSim XE vcom 5.5e_p1 Compiler 2001.11 Nov 16 2001
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package p_aclk
# -- Compiling package p_disclk
# Cannot open file: work/p_disclk/_primary.dat
# ERROR: C:/VHDL_Pack/P_DISCLK.VHD(11): VHDL Compiler exiting
# ERROR: c:/Modeltech_xe/win32xoem/vcom failed.
# Error in macro ./tb_alarm_reg.fdo line 6
# c:/Modeltech_xe/win32xoem/vcom failed.
#     while executing
# "vcom -skip e -93 -explicit   -work work C:/VHDL_Pack/P_DISCLK.VHD"
Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.vcom -reportprogress 300 -work work {C:/VHDL_Pack/P_DISCLK.VHD}
# Model Technology ModelSim XE vcom 5.5e_p1 Compiler 2001.11 Nov 16 2001
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package p_aclk
# -- Compiling package p_disclk
# -- Loading package textio
# -- Compiling package body p_disclk
# -- Loading package p_disclk
do tb_alarm_reg.fdo
# Model Technology ModelSim XE vcom 5.5e_p1 Compiler 2001.11 Nov 16 2001
# Model Technology ModelSim XE vcom 5.5e_p1 Compiler 2001.11 Nov 16 2001
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package p_aclk
# -- Compiling package p_disclk
# -- Loading package textio
# -- Compiling package body p_disclk
# -- Loading package p_disclk
# WARNING[10]: C:/VHDL_Pack/P_DISCLK.VHD(42): Using 1076-1987 syntax for file declaration.
# Model Technology ModelSim XE vcom 5.5e_p1 Compiler 2001.11 Nov 16 2001
# Model Technology ModelSim XE vcom 5.5e_p1 Compiler 2001.11 Nov 16 2001
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling package p_aclk
# Model Technology ModelSim XE vcom 5.5e_p1 Compiler 2001.11 Nov 16 2001
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package p_aclk
# -- Compiling entity alarm_reg
# Model Technology ModelSim XE vcom 5.5e_p1 Compiler 2001.11 Nov 16 2001
# -- Loading package standard
# -- Compiling architecture behavioral of alarm_reg
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package p_aclk
# -- Loading entity alarm_reg
# Model Technology ModelSim XE vcom 5.5e_p1 Compiler 2001.11 Nov 16 2001
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package p_aclk
# -- Compiling entity testbench
# Model Technology ModelSim XE vcom 5.5e_p1 Compiler 2001.11 Nov 16 2001
# -- Loading package standard
# -- Compiling architecture behavior of testbench
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package p_aclk
# -- Loading entity testbench
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading entity alarm_reg
# vsim -lib work -t 1ps -L xilinxcorelib testbench 
# Loading c:/Modeltech_xe/win32xoem/../std.standard
# Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body)
# Loading c:/Modeltech_xe/win32xoem/../ieee.numeric_std(body)
# Loading work.p_aclk
# Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body)
# Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body)
# Loading work.testbench(behavior)
# Loading work.alarm_reg(behavioral)
# .wave
# .structure
# .signals
run 200ns
exit
