.include "lab7FINAL.jsim" .include "nominal.jsim" .include "lab6checkoff.jsim" .subckt beta clk reset ia[31:0] id[31:0] ma[31:0] + moe mrd[31:0] wr mwd[31:0] Xpc clk reset ia[31:0] pc XregFile clk werf ra2sel id[20:16] id[15:11] id[25:21] wdata[31:0] radata[31:0] rbdata[31:0] regfile Xctl reset id[31:26] ra2sel bsel alufn[5:0] wdsel werf moe mwe ctl Xbsel1 bsel#16 rbdata[31:16] id15#16 b[31:16] mux2 Xbsel2 bsel#16 rbdata[15:0] id[15:0] b[15:0] mux2 Xalu alufn[5:0] radata[31:0] b[31:0] ALU[31:0] ALU XmuxWDSEL wdsel#32 ALU[31:0] mrd[31:0] wdata[31:0] mux2 .ends .subckt pc clk reset ia[31:0] Xmux reset#30 s[31:2] 0#30 ia[31:2] mux2 .connect ia[1:0] 0 .connect o[1:0] 0 Xdreg ia[31:2] clk#30 o[31:2] dreg Xone one constant1 Xadd4 o2 one 0 s2 c2 FA Xadd o[31:3] 0#29 c[30:2] s[31:3] c[31:3] FA *Wt add4[31:0] nrz(0v,5.0v,50ns,0ns,.1ns,.1ns) 4 *X32add o[31:0] add4[31:0] s[31:0] 0 v z n 32BITADDER .ends .subckt regfile clk werf ra2sel ra[4:0] rb[4:0] rc[4:0] + wdata[31:0] radata[31:0] rbdata[31:0] Xmux ra2sel#5 rb[4:0] rc[4:0] ra2mux[4:0] mux2 Xregfile + vdd 0 0 ra[4:0] adata[31:0] + vdd 0 0 ra2mux[4:0] bdata[31:0] + 0 clk werf rc[4:0] wdata[31:0] + $memory width=32 nlocations=31 //for r31 = 0 //for a Xand4a ra[4:1] a1 and4 Xand2a a1 ra0 a2 and2 XmuxA a2#32 adata[31:0] 0#32 radata[31:0] mux2 //for b Xand4b ra2mux[4:1] b1 and4 Xand2b b1 ra2mux0 b2 and2 XmuxB b2#32 bdata[31:0] 0#32 rbdata[31:0] mux2 //.connect adata[31:0] radata[31:0] //.connect bdata[31:0] rbdata[31:0] .ends .subckt ctl reset id[31:26] ra2sel bsel alufn[5:0] wdsel werf moe mwe *// WERF *Xstore id30 id29 id26 store and3 *XinvWERF store werf inverter Xctl vdd 0 0 id[31:26] // one read port + ra2sel bsel alufn[5:0] wdsel werf moe xwr + $memory width=12 nlocations=64 contents=( + 0b000000000000 // opcode = 0b000000 + 0b000000000000 // opcode = 0b000001 + 0b000000000000 // opcode = 0b000010 + 0b000000000000 // opcode = 0b000011 + 0b000000000000 // opcode = 0b000100 + 0b000000000000 // opcode = 0b000101 + 0b000000000000 // opcode = 0b000110 + 0b000000000000 // opcode = 0b000111 + 0b000000000000 // opcode = 0b001000 + 0b000000000000 // opcode = 0b001001 + 0b000000000000 // opcode = 0b001010 + 0b000000000000 // opcode = 0b001011 + 0b000000000000 // opcode = 0b001100 + 0b000000000000 // opcode = 0b001101 + 0b000000000000 // opcode = 0b001110 + 0b000000000000 // opcode = 0b001111 + 0b000000000000 // opcode = 0b010000 + 0b000000000000 // opcode = 0b010001 + 0b000000000000 // opcode = 0b010010 + 0b000000000000 // opcode = 0b010011 + 0b000000000000 // opcode = 0b010100 + 0b000000000000 // opcode = 0b010101 + 0b000000000000 // opcode = 0b010110 + 0b000000000000 // opcode = 0b010111 + 0b010000001110 // opcode = 0b011000 LD // check MOE + 0b110000000001 // opcode = 0b011001 ST // check MOE + 0b000000000000 // opcode = 0b011010 + 0b000000000000 // opcode = 0b011011 + 0b000000000000 // opcode = 0b011100 + 0b000000000000 // opcode = 0b011101 + 0b000000000000 // opcode = 0b011110 + 0b000000000000 // opcode = 0b011111 + 0b000000000100 // opcode = 0b100000 ADD + 0b000000010100 // opcode = 0b100001 SUB + 0b000000000000 // opcode = 0b100010 + 0b000000000000 // opcode = 0b100011 + 0b001100110100 // opcode = 0b100100 CMPEQ + 0b001101010100 // opcode = 0b100101 CMPLT + 0b001101110100 // opcode = 0b100110 CMPLE + 0b000000000000 // opcode = 0b100111 + 0b000110000100 // opcode = 0b101000 AND + 0b000111100100 // opcode = 0b101001 OR + 0b000101100100 // opcode = 0b101010 XOR + 0b000000000000 // opcode = 0b101011 + 0b001000000100 // opcode = 0b101100 SHL + 0b001000010100 // opcode = 0b101101 SHR + 0b001000110100 // opcode = 0b101110 SRA + 0b000000000000 // opcode = 0b101111 + 0b010000000100 // opcode = 0b110000 ADDC + 0b010000010100 // opcode = 0b110001 SUBC + 0b000000000000 // opcode = 0b110010 + 0b000000000000 // opcode = 0b110011 + 0b011100110100 // opcode = 0b110100 CMPEQC + 0b011101010100 // opcode = 0b110101 CMPLTC + 0b011101110100 // opcode = 0b110110 CMPLEC + 0b000000000000 // opcode = 0b110111 + 0b010110000100 // opcode = 0b111000 ANDC + 0b010111100100 // opcode = 0b111001 ORC + 0b010101100100 // opcode = 0b111010 XORC + 0b000000000000 // opcode = 0b111011 + 0b011000000100 // opcode = 0b111100 SHLC + 0b011000010100 // opcode = 0b111101 SHRC + 0b011000110100 // opcode = 0b111110 SRAC + 0b000000000000 // opcode = 0b111111 + ) Xzero zero constant0 XmuxWR reset xwr zero mwe mux2 .ends