| Opcode | Mnemonic | Meaning | Address Mode | Status Bits |
|
00000 |
STOP |
Stop Execution |
U |
|
|
00001 |
LOADR |
R := Oprnd |
idsx |
NZ |
|
00010 |
STORER |
Oprnd := R |
dsx |
|
|
00011 |
ADDR |
R := R + Oprnd |
idsx |
NZVC |
|
00100 |
SUBR |
R := R - Oprnd |
idsx |
NZVC |
|
00101 |
ANDR |
R := R AND Oprnd |
idsx |
NZ |
|
00110 |
ORR |
R := R OR Oprnd |
idsx |
NZ |
|
00111 |
NOTR |
R := NOT R |
U |
NZ |
|
01000 |
ASLR |
C := most significant bit R := arithmetic shift left R |
U |
NZVC |
| 01001 | ASRR | C := least significant bit R := arithmetic shift right R |
U | NZC |
| 01010 | LDBYTR | R := byte Oprnd | idsx | NZ |
| 01011 | STBYTR | byte Oprnd := R | dsx | |
| 01100 | LOADB | B := Oprnd | idsx | NZ |
| 01101 | ADDSP | SP := SP + Oprnd | i | NZVC |
| 01110 | BR | PC := Oprnd | ix | |
| 01111 | BRLE | if NZVC = <= then PC := Oprnd | ix | |
| 10000 | BRLT | if NZVC = < then PC := Oprnd | ix | |
| 10001 | BREQ | if NZVC = = then PC := Oprnd | ix | |
| 10010 | BRNE | if NZVC = /= then PC := Oprnd | ix | |
| 10011 | BRGE | if NZVC = >= then PC := Oprnd | ix | |
| 10100 | BRGT | if NZVC = > then PC := Oprnd | ix | |
| 10101 | BRV | if V = 1 then PC := Oprnd | ix | |
| 10110 | BRC | if C = 1 then PC := Oprnd | ix | |
| 10111 | COMPR | R - Oprnd | idsx | NZVC |
| 11000 | JSR | SP := SP -2 Mem[SP] := PC PC := Oprnd |
ix | |
| 11001 | RTS | PC := Mem[SP] SP := SP +2 |
U | |
| 11010 | RTI | return from interrupt | U | |
| 11011 | CHARI | byte Oprnd := input | dsx | |
| 11100 | CHARO | output := byte Oprnd | idsx | |
| 11101 | DECI | Oprnd := input | dsx | NZV |
| 11110 | DECO | output := Oprnd | idsx | |
|
11111 |
HEXO |
output := Oprnd |
idsx |
|