John T. Robinson
[email protected]
Summary
An interesting problem is one where it is not known in advance how
(or even if) the problem can be solved (as opposed to engineering problems,
although engineering problems often turn out to be interesting
for various reasons): I like working on interesting problems.
Previously I have worked on problems
related to the design, analysis, testing, and verification of novel computer
software and hardware systems. I have a broad background in these fields,
with over thirty years experience in areas including database and
operating systems, parallel and distributed algorithms and systems,
storage hierarchies and systems, buffer and cache management,
data visualization, performance analysis, compression technology,
and hardware design verification.
Currently I am available for work on interesting problems in either
full or part time (for example visiting or consulting) positions,
and also just for fun (for example on problems that have no
obvious commercial potential but are nevertheless interesting).
Education
Stanford University (1971-1974): B.S. with Distinction, Mathematics
I completed the four year program in three years, taking introductory graduate level
courses during my last year; also during my last year I worked part time for the
Stanford High Energy Physics Laboratory, and full time for one year (1974-1975)
after graduation.
Carnegie-Mellon University (1975-1981): Ph.D. in Computer Science
My first research project led to publication of both conference and journal papers
(analysis of algorithms for asynchronous multiprocessors). As a research assistant I
developed optimistic methods for concurrency control (the starting point for my thesis
work) and K-D-B-trees. I also worked as a teaching assistant for various undergraduate
computer science courses. My thesis was Design of Concurrency Controls for
Transaction Processing Systems; as part of this work
I implemented a complete transaction processing system on the CMU 50-way
Cm* multi-microprocessor.
Professional Experience
IBM Research Division (1981-June 2005): Research Staff Member
In one of my first projects I developed microcode for a shared disk control unit that
implemented a programmable general-purpose locking facility; this was used to develop
a working prototype of an IMS multi-system data sharing system with fast locking. Since
then I have been involved in a wide variety of different projects, ranging from theory
and performance analysis to prototype development, in both hardware and software
areas. More recently I have worked on hardware design and verification, compressed
memory system design and analysis, storage provisioning in storage area networks,
processor cache design, and design and analysis of SMP coherency protocols.
My major strengths are system design, performance analysis, and implementation.
I generally consider programming languages simply as tools, and have programmed in
virtually every major programming and scripting language (although primarily in C
for recent work). I have over thirty conference and journal publications,
thirty issued patents, and four pending patents.
Career Highlights
Some of my more well-known past work (for example see
http://scholar.google.com/scholar?q="john+t+robinson") includes:
- Optimistic methods for concurrency control;
- K-D-B-trees (the first generalization of B-trees to the multi-dimensional case);
- Frequency based replacement (FBR - the starting point for a number of subsequent
improvements to LRU buffer management);
- Analysis of limitations of concurrency; and
- Concurrency control methods for high contention environments.
One of my major contributions within IBM was work on the design and analysis of
parallel compression methods and compressed memory systems; this work was part of
the basis for the IBM MXT (memory expansion technology) compressed memory system
product. My IBM awards include an Outstanding Innovation Award for work on concurrency
control for high contention environments, and two Research Division Awards. My most
recent IBM invention achievement awards were for the tenth and eleventh plateaus
(December 2004 and January 2006). I have
had two IBM top-5% and one top-30% rated patent awards, and was an IBM Master Inventor
from 1999-2002. Currently I have 33 entries in the
DBLP Bibliography Server; here is my
ACM Author Profile page.
Recent Work
- 7/2005 - present: Completion of in-progress work (patent applications;
publications); independent work on various problems
including analysis of algorithms using continuous approximations and
analysis of cache line replacement selection methods (including
generalized tree-LRU); studies of problem solving techniques
(such as those appearing on "problem of the month" web sites); preliminary
research and writing of proposals for small business innovative project
funding initiatives (in progress).
- 2004-6/2005: L2 cache micro-architecture design and NMP (near memory processor)
design for the PERCS project (DARPA contract project) - editor and major contributor
for L2 section of 2004 milestone document; design and evaluation of new approaches to
cache architectures including overflow cache, cache bypass, generalized tree-LRU
replacement, and non-uniform cache architectures; evaluation of these using IBM
Rochester's cache simulator tools and IBM Austin's MAMBO execution-driven simulator;
evaluation of Power6 and planned P7 cache coherency protocols;
also evaluation of use of memory compression technology in PowerPC architectures.
- 2003: Work in storage systems and storage area networks; led successful effort to
integrate Lodestone product with the A-Tango storage provisioning environment;
performance analysis of storage provisioning methods, and completion of demo system
for demand-based automated storage provisioning.
- 2001-2002: Logic verification for Katsina-2 (planned MXT follow on product) -
independently developed emulator along with test case generators to verify operation
of the memory compression/decompression, CRC generation, translation table, and
memory management hardware; integrated into logic verification environment; due to
complexity of hardware this approach allowed numerous design errors to be discovered;
at the completion of the project all tests were running correctly (note: the MXT product
is described in a number of papers, for example see the three IBM J.R&D papers
from March 2001 referenced below).
- 1999-2000: Compressed memory system architecture - design and performance analysis
of a number of novel approaches to compressed memory system design; this work led to
several patent applications, a publication, and was integrated into the IBM Rochester
Pecos system design.
- 1996-1998: (1) Development (with Peter Franaszek) of parallel compression using
a shared dictionary and methods for memory management in compressed memory systems;
independently development of high-level hardware design for compressor/de-compressor
and performance analysis of compressed memory (this work was the basis for the MXT
product); (2) independent development of the variable resolution (software) compression
component (based on arithmetic coding) for the NASA contract project for content-based
retrieval of digital images (joint work with IBM Boulder); (3) development (with
Peter Franaszek) and independent performance analysis of methods for variable scope
of parity protection in disk arrays (note: all of the foregoing resulted in a number
of issued patents and publications).
Patents (4 pending; 30 issued)
- U.S. Patent No. 7,454,573.
With A. Buyuktosunoglu, Z. Hu, J. Rivers, X. Shen, and V. Srinivasan.
Cost-Conscious Pre-emptive Cache Line Displacement and Relocation Mechanisms.
Nov. 18, 2008.
- U.S. Patent No. 7,395,373.
Set-Associative Cache using Cache Line Decay Counts and Set Overflow.
July 1, 2008.
- U.S. Patent No. 7,254,578.
With M. Devarakonda.
Concurrency Classes for Shared File Systems.
August 7, 2007.
- U.S. Patent No. 7,228,388.
With Z. Hu, X. Shen, and B. Sinharoy.
Enabling and Disabling Cache Bypass using Predicted Cache Line Usage.
June 5, 2007.
- U.S. Patent No. 7,103,722.
With C. Benveniste, P. Franaszek, and C. Schulz.
Cache Configuration for Compressed Memory Systems.
Sept. 5, 2006.
- U.S. Patent No. 7,039,769.
With V. Castelli, P. Franaszek, and P. Heidelberger.
Direct Addressed Shared Compressed Memory System.
May 2, 2006.
- With C. Gonzales, Z. Chen, D. Poff, and B. Iyer.
Method and Apparatus for Increasing Virtual Storage Capacity in On-Demand
Storage Systems.
Filed 12/23/05.
- U.S. Patent No. 6,961,821.
Reconfigurable Cache Controller for Nonuniform Memory Access Computer Systems.
Nov. 1, 2005.
- U.S. Patent No. 6,901,483. With B. Tremaine and M. Wazlowski.
Prioritizing and Locking Removed and Subsequently Reloaded Cache Lines.
May 31, 2005.
- With A. Buyuktosunoglu, Z. Hu, J. Rivers, X. Shen, V. Srinivasan.
Arrangements for Reducing Latency and Snooping Cost in Non-Uniform Cache Memory
Architectures. Filed 4/29/05.
- With M. Wazlowski.
Computer-based Communication and Arrangements Associated Therewith for
Indicating User Status.
Filed 11/19/04.
- With L. Lastras and P. Franaszek.
Data Compression using a Nested Hierarchy of Fixed Phrase Length Dictionaries.
Filed 11/16/04.
- U.S. Patent No. 6,779,088.
With C. Benveniste and P. Franaszek.
Virtual Uncompressed Cache Size Control in Compressed Memory Systems.
Aug. 17, 2004.
- U.S. Patent No. 6,587,923.
With C. Benveniste and P. Franaszek.
Dual Line Size Cache Directory.
July 1, 2003.
- U.S. Patent No. 6,539,460.
With V. Castelli, P. Franaszek, and P. Heidelberger.
System and Method for Storing Data Sectors with Header and Trailer Information in a
Disk Cache Supporting Memory Compression.
March 25, 2003.
- U.S. Patent No. 6,385,699.
With G. Bozman and W. Tetzlaff.
Managing an Object Store based on Object Replacement Penalties and
Reference Probabilities.
May 7, 2002.
- U.S. Patent No. 6,353,871.
With C. Benveniste, P. Franaszek, and C. Schulz.
Directory Cache for Indirectly Addressed Main Memory.
Mar. 5, 2002.
- U.S. Patent No. 6,349,372.
With C. Benveniste, P. Franaszek, and C. Schulz.
Virtual Uncompressed Cache for Compressed Main Memory.
Feb. 19, 2002.
- U.S. Patent No.s 6,343,350, and 6,378,053.
With R. LaMaire.
Conserving Storage Space by Means of Low Resolution Objects.
Jan. 29, 2002, and April 23, 2002.
- U.S. Patent No. 6,341,325.
With P. Franaszek.
Method and Apparatus for Addressing Main Memory Contents Including a Directory
Structure in a Computer System.
Jan. 22, 2002.
- U.S. Patent No.s 6,021,224, and 6,141,445.
With V. Castelli, I. Kontoyiannis, and J. Turek.
Multiresolution Lossless/Lossy Compression and Storage of Data for Efficient
Processing Thereof.
Feb. 1, 2000, and Oct. 31, 2000.
- U.S. Patent No. 6,005,971.
With L. Bergman, J. Gerth, and B. Rogowitz.
Method, System and Program Products for Displaying Multiple Types of
Data in Single Images.
Dec. 21, 1999.
- U.S. Patent No. 5,978,788.
With V. Castelli, A. Jhingran, and C.S. Li.
System and Method for Generating Multi-Representations of a Data Cube.
Nov. 2, 1999.
- U.S. Patent No. 5,870,036.
With P. Franaszek and J. Thomas.
Adaptive Multiple Dictionary Data Compression.
Feb. 9, 1999.
- U.S. Patent No.s 5,708,793, and 5,860,103.
With P. Franaszek.
Method and Apparatus using Address and Read Head Location Information to
Provide Optimal Operation of a Disk System.
Jan. 13, 1998, and Jan. 12, 1999.
- U.S. Patent No. 5,737,558.
With J. Knight.
Multi-Column Windows.
Apr. 7, 1998.
- U.S. Patent No. 5,729,228.
With P. Franaszek and J. Thomas.
Parallel Compression and Decompression using a Cooperative Dictionary.
Mar. 17, 1998.
- U.S. Patent No. 5,522,032.
With P. Franaszek and A. Thomasian.
RAID Level 5 with Free Blocks Parity Cache.
May 28, 1996.
- U.S. Patent No. 5,193,188.
With P. Franaszek and A. Thomasian.
Centralized and Distributed Wait Depth Limited Concurrency Control
Methods and Apparatus.
Mar. 9, 1993.
- U.S. Patent No. 5,043,885.
Data Cache using Dynamic Frequency Based Replacement and Boundary Criteria.
Aug. 27, 1991.
- U.S. Patent No. 4,709,326.
General Locking/Synchronization Facility with Canonical States and
Mapping of Processors.
Nov. 24, 1987.
Publications
Journal Publications (15)
- With C. Benveniste and P. Franaszek.
Cache-memory interfaces in compressed memory systems.
IEEE Trans. Computers 50, 11 (Nov. 2001), 1106-1116.
- With P. Franaszek, P. Heidelberger, and D. Poff.
Algorithms and data structures for compressed-memory machines.
IBM Journal of Res. & Develop. 45, 2 (March 2001), 245-258.
- With P. Franaszek.
On internal organization in compressed random access memories.
IBM Journal of Res. & Develop. 45, 2 (March 2001), 259-270.
- With R. B. Tremaine, P. A. Franaszek, C. O. Schulz, T. B. Smith,
M. E. Wazlowski, and P. M. Bland.
IBM Memory Expansion Technology (MXT).
IBM Journal of Res. & Develop. 45, 2 (March 2001), 271-285.
- With V. Castelli, L. Bergman, I. Kontoyiannis, C.-S. Li, and J. Turek.
Progressive search and retrieval in large image archives.
IBM Journal of Res. & Develop. 42, 2 (March 1998), 253-268.
- With P. Franaszek.
On variable scope of parity protection in disk arrays.
IEEE Trans. Computers 46, 2 (Feb. 1997), 234-240.
- With P. Franaszek, J. R. Haritsa, and A. Thomasian.
Distributed concurrency control based on limited wait-depth.
IEEE Trans. Parallel and Distributed Systems 4, 11 (Nov. 1993), 1246-1264.
- With P. Franaszek and A. Thomasian.
Concurrency control for high contention environments.
ACM Trans. Database Systems 17, 2 (June 1992), 304-345.
- With P. Heidelberger and A. Norton.
Parallel quicksort using fetch-and-add.
IEEE Trans. Computers 39, 1 (Jan. 1990), 133-138.
- With D. Dias, B. Iyer, and P. Yu.
Integrated concurrency-coherency controls for multi-system data sharing.
IEEE Trans. Soft. Eng. 15, 4 (April 1989), 437-448.
- With P. Yu, D. Dias, B. Iyer, and D. Cornell.
On coupling multi-systems through data sharing.
Proceedings of the IEEE 75, 5 (May 1987), 573-587.
- With P. Franaszek.
Limitations of concurrency in transaction processing.
ACM Trans. Database Systems 10, 1 (March 1985), 1-28.
- Separating policy from correctness in concurrency control design.
Software-Practice and Experience 14, 9 (Sept. 1984), 827-844.
- With H. T. Kung.
On optimistic methods for concurrency control.
ACM Trans. Database Systems 6, 2 (June 1981), 213-226.
- Some analysis techniques for asynchronous multiprocessor algorithms.
IEEE Trans. Soft. Eng. SE-5, 1 (Jan. 1979), 24-31.
Conference Publications (16)
- With P. Franaszek, L. Lastras, and S. Peng.
Data compression with restricted parsings.
In Proc. DCC 2006 Data Compression Conf., pp. 203-212, IEEE, 2006.
- With P. Franaszek and J. Thomas.
Parallel compression with cooperative dictionary construction.
In Proc. DCC 1996 Data Compression Conf., pp. 200-209, IEEE, 1996.
- With P. Franaszek.
Analysis of reorganization overhead in log-structured file systems.
In Proc. 10th Int. Conf. Data Engineering, pp. 102-110, IEEE, 1994.
- With P. Franaszek, J. R. Haritsa, and A. Thomasian.
Distributed concurrency control with limited wait depth.
In Proc. 12th Int. Conf. Distributed Computing Systems, pp. 160-167, IEEE, 1992.
- With P. Franaszek and A. Thomasian.
Wait depth limited concurrency control.
In Proc. 7th Int. Conf. Data Engineering, pp. 92-101, IEEE, 1991.
- With M. Devarakonda.
Data cache management using frequency-based replacement.
In Proc. 1990 ACM SIGMETRICS Conf., pp. 134-142, ACM, 1990.
- With P. Franaszek and A. Thomasian.
Access invariance and its use in high contention environments.
In Proc. 6th Int. Conf. Data Engineering, pp. 47-55, IEEE, 1990.
- With D. Dias, B. Iyer, and P. Yu.
Design and analysis of integrated concurrency-coherency controls.
In Proc. 13th VLDB Conf., pp. 463-471, VLDB, 1987.
- Order preserving linear hashing using dynamic key statistics.
In Proc. 5th ACM SIGACT-SIGMOD Symp. Principles of Database Systems,
pp. 91-99, ACM, 1986.
- With P. Yu, D. Dias, B. Iyer, and D. Cornell.
Distributed concurrency control analysis for data sharing.
In Proc. 16th Computer Measurement Group Conf., pp. 13-20, CMG, 1985.
- A fast general-purpose hardware synchronization mechanism.
In Proc. ACM-SIGMOD 1985 Int. Conf. Management of Data, pp. 122-130, ACM, 1985.
- With P. Yu, D. Dias, B. Iyer, and D. Cornell.
Modeling of centralized concurrency control in a multi-system environment.
In Proc. 1985 ACM SIGMETRICS Conf., pp. 183-191, ACM, 1985.
- With H. F. Korth, R. Krishnamurthy, and A. Nigam.
A framework for understanding distributed (deadlock detection) algorithms.
In Proc. 2nd ACM SIGACT-SIGMOD Symp. Principles of Database Systems,
pp. 192-202, ACM, 1983.
- The K-D-B-tree: a search structure for large multidimensional dynamic indexes.
In Proc. ACM-SIGMOD 1981 Int. Conf. Management of Data, pp. 10-18, ACM, 1981.
- With H. T. Kung.
On optimistic methods for concurrency control.
In Proc. Fifth Int. Conf. Very Large Databases, p. 351, IEEE, 1979.
- Analysis of asynchronous multiprocessor algorithms with applications to sorting.
In Proc. 1977 Int. Conf. on Parallel Processing, pp. 128-135, IEEE, 1977.
Other Selected Publications
- With P. Franaszek, L. Lastras, and S. Peng.
Data compression with restricted parsings.
Report RC 23804, IBM Watson Res. Ctr., Yorktown Hts. NY,
Nov. 16, 2005.
- Generalized tree-LRU replacement.
Report RC 23332, IBM Watson Res. Ctr., Yorktown Hts. NY, 2004.
- With P. Franaszek.
Design and analysis of internal organizations for compressed random access memories.
Report RC 21146, IBM Watson Res. Ctr., Yorktown Hts. NY, 1998.
- With M. Devarakonda.
Note on a problem with Reed and Long's FBR results.
Operating Systems Review 31, 1 (Jan. 1997), 3-4.
- Analysis of steady-state segment storage utilizations in a log-structured
file system with least-utilized segment cleaning.
Operating Systems Review 30, 4 (Oct. 1996), 29-32.
- With L. Bergman et al.
Progressive search and retrieval in large image archives.
Report RC 20583, IBM Watson Res. Ctr., Yorktown Hts. NY, 1996.
- With J. Turek et al.
Search and retrieval in large image archives.
Report RC 20214, IBM Watson Res. Ctr., Yorktown Hts. NY, 1995.
- Some further analysis of the essential blocking recurrence.
SIGMOD Record 20, 1 (March 1991), 9-11.
- Experiments with transaction processing on a multi-microprocessor.
Report RC 9725, IBM Watson Res. Ctr., Yorktown Hts. NY, 1982.
- Design of Concurrency Controls for Transaction Processing Systems.
Ph.D. Thesis, Report CMU-CS-82-114, Carnegie-Mellon Univ., Pittsburgh PA, 1982.
IP.com articles (37) (technical disclosures available from
www.ip.com)
-
Cache Line Replacement Selection using a Logical Multi-Way Tree with Access
Order States Maintained at Each Node,
IPCOM000030586D, Aug. 18, 2004.
-
User Interface for Controlling and Originating One-to-One, One-to-Many,
Many-to-One, and Many-to-Many Communication Sessions,
IPCOM000029026D, June 11, 2004.
-
Method for Prefetching Cache Lines Based on the Presence of Uninitialized Lines,
IPCOM000027339D, April 7, 2004.
-
Method for Annotating Object Lists in Computer Systems,
IPCOM000019893D, Oct. 7, 2003.
-
With K. Wu.
Workstation Power-up Speech Synthesized Error Messages,
IPCOM000114857D, Feb. 1995.
-
Efficient In-Place Reordering of Virtual Memory Data.
IPCOM000113145D, July 1994.
-
With P. Franaszek and A. Thomasian
Reorganizing Data in Log Structured File Systems,
IPCOM000112798D, June 1994.
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Virtual Record Memory,
IPCOM000110813D, Jan. 1994.
-
With B. Bennett.
Sorting Large Multi-Volume Datasets using Data Pipes,
IPCOM000106770D, Dec. 1993.
-
With B. Bennett.
Method of Merging with a Coprocessor,
IPCOM000105353D, July 1993.
-
With J. Knight.
Cache Type Files,
IPCOM000105001D, June 1993.
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Virtual Relational Memory,
IPCOM000104453D, April 1993.
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In-Place Reordering of Data using a Double Buffer,
IPCOM000104324D, April 1993.
-
With P. Franaszek and A. Thomasian.
Extended Older Priority Concurrency Control,
IPCOM000107366D, Feb. 1992.
-
With M. Devarakonda.
Multi-Section Method for Data Cache Management,
IPCOM000120618D, May 1991.
-
With J. Antognini, B. Bennett, M. Sachs, and W. Tetzlaff.
Parallel Long Move Instruction,
IPCOM000119801D, March 1991.
-
With P. Franaszek and A. Thomasian.
Adaptive Concurrency Control Scheme for Transaction Processing,
IPCOM000119558D, Feb. 1991.
-
With P. Franaszek and A. Thomasian.
Two-Phase Running Priority Method for Transaction Processing,
IPCOM000119561D, Feb. 1991.
-
With P. Franaszek and A. Thomasian.
Integrated Concurrency Control/CPU Scheduling,
IPCOM000119563D, Feb. 1991.
-
With P. Franaszek and P. Heidelberger.
Spawning Method for Transaction Processing,
IPCOM000119626D, Feb. 1991.
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Vector Partitioning Apparatus,
IPCOM000099701D, Feb. 1990.
-
With P. Franaszek.
Two Phase Method for Transaction Processing,
IPCOM000037344D, Dec. 1989.
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With H. Stone.
Means for Reducing Collisions in a Multiprocessor
Interconnection Network,
IPCOM000036193D, Sept. 1989.
-
With P. Heidelberger and A. Nigam.
Parallel Index Scan using Fetch-and-Add in Multiprocessing,
IPCOM000057711D, June 1988.
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With P. Heidelberger and A. Norton.
Efficient Parallel Quicksort using Fetch-and-Add in Multi-Processor
Computing Systems,
IPCOM000057709D, June 1988.
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Shared Object Server for Multi-User Computer Workstations,
IPCOM000057700D, June 1988.
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With A. Thomasian and P. Yu.
Elimination of Lock Contention in Relational
Databases Accessed by Read-Only Queries and Online Update Transactions,
IPCOM000057634D, June 1988.
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Differential Index Management with Low Priority Batch Updating
in Database Management Systems,
IPCOM000057627D, June 1988.
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Maintaining Physical Sequentiality of Dynamic
Key-Associative Key-Sequential Computer Files,
IPCOM000057012D, Feb. 1988.
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Order-Preserving Hashing using Positional Character Transition
Frequencies,
IPCOM000039232D, May 1987.
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Broadcast of Mostly-Read-Only Highly Shared Cache Lines
in Multiprocessor Systems,
IPCOM000039210D, May 1987.
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Method for Scheduling Writes in a Duplexed DASD Subsystem,
IPCOM000062103D, Oct. 1986.
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With D. Dias, B. Iyer, and P. Yu.
Integrated Concurrency and Shared Buffer Coherency Control
for Multi-Systems,
IPCOM000060385D, March 1986.
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Multi-Level GTEO Storage Allocation,
IPCOM000063377D, March 1985.
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With B. Bennett, P. Franaszek, and P. Yu.
Check On Access via Hierarchical Block Validation,
IPCOM000044329D, Dec. 1984.
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Shared Record Validity Checker Control Unit Extension,
IPCOM000043977D, Oct. 1984.
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K-D-Tree Splitting Algorithm,
IPCOM000043969D, Oct. 1984.
Awards
- Selected as ACM Senior Member, February 2009.
- Eleventh Plateau Invention Achievement Award, January 2006.
- Tenth Plateau Invention Achievement Award, November 2004.
- Research Division Award, IBM Memory Expansion Technology (MXT), September 2003.
- Ninth Plateau Invention Achievement Award, February 2003.
- IBM Master Inventor, 1999-2002.
- Eighth Plateau Invention Achievement Award, July 2002.
- Seventh Plateau Invention Achievement Award, June 2000.
- Top 5% Award (U.S. Patent No. 5,729,228, with P. Franaszek and J. Thomas,
Parallel Compression and Decompression using a Cooperative Dictionary,
Mar. 1998), May 1999.
- Top 30% Award (U.S. Patent No. 5,737,558, with J. Knight,
Multi-Column Windows, Apr. 1998), May 1999.
- Sixth Plateau Invention Achievement Award, May 1998.
- Top 5% Award (U.S. Patent No. 5,522,032, with P. Franaszek and A. Thomasian,
RAID Level 5 with Free Blocks Parity Cache, May 1996), May 1997.
- Fifth Plateau Invention Achievement Award, December 1996.
- Fourth Plateau Invention Achievement Award, April 1995.
- Third Plateau Invention Achievement Award, August 1992.
- Outstanding Innovation Award, Concurrency Control Algorithms for
High Contention Environments, March 1990.
- Second Plateau Invention Achievement Award, August 1989.
- First Plateau Invention Achievement Award, May 1987.
- Research Division Award, Multi-System Information Management System Analysis,
May 1986.
- First Patent Application Award, General Locking/Synchronization Facility
(issued as U.S. Patent No. 4,709,326, Nov. 1987), June 1984.