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                          Work Place

                                  I am working as software developer in   SOFTJIN

                                                                  
                                                       Project - 1

          Name     :   RTL Inference Engine
                                                                  
                   Client     :     Fujitsu Lab USA.


                    Purpose :  
                             Fujitsu has  one equivalance checker tool  named as  "assure" 
                which   is  used  to  check whether  two   networks are equal or not. Actually 
                that tool will  work if the  inputs  are inform of  netlist. It will  not work  if there
                is  RTL  in the code.  Our project was to infer logic for the  RTL present in the
                code before doing equivalance  check by assure.
                                 
                We used  HDLFE tool,  developed by  SASKEN   for  FUJITSU.  The HDLFE  
                reads  Verilog  or  VHDL  file  and  creates  a  CDFG(  Control  and Data Flow
                Graph) database.  We are using  that  CDFG data base to develop  the   required
                netlist.
                                    
                HDLFE   was  supporting  VHDL  and   Verilog 95.   We  added  few "Verilog
                2001"  feature  like,  Generate Statements, unsigned integer in HDLFE.

                                  

                                          Project II

             Name :     Porting FINO to OpenAccess

                   Client : Internal Project

               Purpose:
                Fino stands for "Finite Interactive Netlist Optimizer". Fino is a GUI
                based  tool,  is  used  to  visualize  edif  netlist. We   can  edit  that netlist and
                optimize    it  according  to  our  necessity. It  consists of  three parts  n2s, lae,
                schedit. n2s takes edif netlist and gives  edif  schematic  format.  lae takes edif
                netlist  and  produces  a  GUI,  it shows the netlist in form hierarchy,  where we
                can trace  paths  between different points (instance, pin). We can select one path
                and perform different operations like proning some part and save  into  different
                netlist file. Schedit is used to view edif schematic format. One demerit in fino is
                schematic files are very big compared to their HDL conterpart.

                So we tried to port FINO with open access and we are succed to do it. Now we
                store  the  Verilog netlists in OpenAccess netlist format. n2s reads openaccess
                netlist  format  and  creates  schematic and stores in openaccess block domain
                format. The database created in OpenAccess  block  domain  format is genuine
                one, because we are able to view that by GDSII viewer. lae is also able to read
                openaccess module domain format and produces netlist viewer and editor. We
                can select one path from the whole netlist, perform some necessary operations
                on that selected path and again save it to openaccess format. Schedit is also able
                to read openaccess schematic data and produces schematic viewer.

                                     


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