I grew up in Southern California (Chino) and have been in the Sacramento area for the last 7 years.
I enjoy running and working out and reading fiction in the areas of science, engineering and technology. Checking out live music and hanging out with friends.
I'm interested in VLSI design of integrated circuits and design automation in the areas of: logic/physical partitioning, floorplanning, power grid distribution, standard cell and hard macro placement, global/local clock design, logic synthesis & simulation, physical synthesis, placement, routing, parasitic extraction, delay calculation, static timing analysis, reliability verification, functional verification, and signal integrity. I also spend a measurable amount of time programming in Tcl, Perl, and occasionally C in a Unix/Linux based environment.
DAC
ISPD
ISSCC
ICCAD
ISQED
TAU
Synopsys
Cadence