JEFFREY JABSON
LOGCKT
1. Half – subtracter : A combinational circuit that has:
2. Full – subtracter : A combinational circuit that has: - three inputs are a minuend, I, a subtrahend, J, and a borrow digit, K, transferred from another operation, and two outputs that have a difference without carry, W, between the first digit and the sum of the second digit and the borrow digit, and a new borrow digit, X, and in which the outputs are related to the inputs according to the following table:
FULL SUBTRACTER BLOCK DIAGRAM:
Encoder
A functional unit that has a number of input lines such that not more than one at a time may carry a signal and a number of output lines such that any number may carry signals, and such that the combination of output signals serves as a code to indicate which input line carries the signal.
Decoder
A functional unit that has a number of input lines such that any number may carry signals and a number of output lines such that not more than one at a time may carry a signal and such that the combination of input signals serves as a code to indicate which output line carries the signal.
Counter
A functional unit with a finite number of states each of which represents a number that can be, upon receipt of an appropriate signal, increased [increased or decreased] by unity or by a given constant. This device is usually capable of bringing the represented number to a specified value, for example, zero.
modulo-n counter: A counter in which the number represented reverts to zero in the sequence of counting after reaching a maximum value of n-1.
Flip – flops
Flip-flops are circuits that can maintain their state indefinitely as long as power is supplied, and change their states when directed to by a control input. Flip-flops are given a clock input, which specifies specific moments in time to change state. What makes flip-flops special is that their output is connected back into their input, so that their proceeding state depends on both their current state and their control input. Thus, when analyzing the a flip-flop, we look at its inputs and its current output, or state (usually labelled Q(t)), and from those, determine its next state (usually labelled Q(t+1)).
We will look at 4 types of flip-flops: SR flip-flops, D flip-flops, JK flip-flops, and T flip-flops. They are defined as follows:
SR flip-flop D flip-flop JK flip-flop T flip-flop
Q(t) J K Q(t+1) Q(t) D Q(t+1) Q(t) J K Q(t+1) Q(t) T Q(t+1)
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 1 1 0 0 1 0 0 1 1
0 1 0 1 1 0 0 0 1 0 1 1 0 1
1 1 – 1 1 1 0 1 1 1 1 1 0
0 0 1 1 0 0 1
0 1 0 1 0 1 0
1 1 0 1 1 1 0 1
1 1 1 - 1 1 1 0
The flip-flops as given above change state only when a clock signal is present. However, the clock signal is not necessarily instantaneous, so there needs to be a way to prevent the flip-flop from changing state multiple times during a clock cycle. There are 2 ways to achieve this. One is to only change state once the clock cycle is finished. This type of flip-flop is called a master-slave flip-flop. The other is a flip-flop that only triggers during a signal transition. This type is called an edge-triggered flip-flop.
The master-slave flip-flop works by allowing one flip-flop to change state as the clock pulse is active. The output from that flip-flop goes into another flip-flop, which is attached to an inverted clock input. Thus, the state of the first flip-flop will have settled by the time its output changes the state of the second flip-flop after the clock pulse has finished, and stable output will have been achieved.
Edge Triggered flip-flops
Edge triggered flip-flops trigger only when the pulse is in transition. Some trigger during a positive transition (going from 0-to-1), and are called positive edge triggered flip-flops. Others trigger during a negative transition (going from 1-to-0), and are called negative edge triggered flip-flops.
Multiplexer
A device that receives input signals from various sources and combines them into a single transmission, sending the signals out over one line. In some cases, the multiplexer receiving the signals then reverses the process by separating the signal components from the stream and redistributing them to their respective destinations.
Demultiplexer
A logic circuit that can route a single line of digital information to other lines, the device acting to switch information to many different points.
TTL ( Transistor – Transistor Logic )
TTL devices make use of bipolar transistors. The main distinguishing features of the basic TTL family is that they demand a power rail which is very close to +5V, and they use a relatively high amount of current to drive their logic levels ( below 1V for a logical ‘0’ or ‘low’, and above about 3.5V for a logical ‘1’ or ‘high’ ). A particular characteristic of TTL signals is that the inputs to a gate "float high" — i.e. rise to a logical ‘1’ — if left unconnected. This means that the main requirement for driving a TTL input is to "pull down" the level to near 0V. This typically takes a few milliamps per input. This is usually described by saying that a TTL signal source has to be able to "sink" a relatively large current. Typically, TTL gates take around 10-20 nanoseconds to switch level. Hence we can ‘clock’ TTL and pass bits through the gates at rates up to around 50MHz provided the circuits are designed carefully. With care, speeds approaching 100MHz are possible, but for high speed operation other forms of logic may work better.
As with other kinds of integrated circuits there are many variations on the basic TTL family. The original chips have numbers like "SN74xx", where xx is the part number. In general, the most useful series is the SN74LSxx family. These consume much less current that basic TTL and hence are easier on the power supply. The ‘L’ in the title stands for "low power", and the ‘S’ stands for "Schottky" — the kinds of diode used inside the gates to help them run quickly without using a lot of current. (The diodes prevent the transistors inside the chip from ‘saturating’ when turned on and wasting lots of current.)
74 family |
74LS family |
54 family |
Supply Voltage |
| +5V (+/- 0.5V) | +5V (+/- 0.5V) | +5V (+/- 0.25V) | ‘1’ Level Output Current |
| 0.4mA | 0.4mA | 0.4mA | ‘0’ Level Output Current |
| 16mA | 8mA | 16mA | ‘1’ Level Input Voltage (min) |
| 2V | 2V | 2V | ‘0’ Level Input Voltage (max) |
| 0.8V | 0.8V | 0.8V | ‘1’ Level Input Current |
| 0.04mA | 0.05mA | 0.04mA | ‘0’ Level Input Current |
| 1.6mA | 0.4mA | 1.6mA |
Comparing the above we can see that the main difference between the 74 and 74LS families is that we have to pull (i.e. ‘sink’) around 1.6mA out of a 74 input to hold it down to a logic ‘0’, but we only have to draw 0.4mA out of a 74LS to hold it down. In general, we can expect an LS gate to consume around a quarter the power/current of a plain 74 gate of the same type. Hence the LS gates are a good choice if we are using a battery or want to save on the power supply cost. From the table it is not obvious why anyone would choose the related 54 family as it seems much the same as the 74 one. However, 54 gates are built to operate over a much wider temperature range (-55 Celsius to +125 Celsius) that the 74/74LS (0 to 70 Celsius). Hence the 54 family is better if we have to build circuits for ‘extreme’ environments. TTL is still used a lot when building ‘one off’ logic circuits as the gates are cheap and fairly robust (i.e. you aren't likely to damage them when building the circuit!). However, most modern large scale commercial and industrial systems use CMOS logic as it is cheaper/better for integrated systems. The main disadvantage of CMOS is that it is static sensitive, hence it can be depressingly easy to destroy CMOS logic simply by taking it out of its package carelessly!!
2.) Description of TTL Logic Families
TTL (74xx) True TTL
74L......................Low power
74S......................Schottky
74H......................High speed
74LS....................Low power - Schottky
74AS...................Advanced - Schottky
74ALS.................Advanced - Low power - Schottky
74F(AST).............Fast - (Advanced - Schottky)
74C......................CMOS.......check Vcc level
74HC (U).............High speed - CMOS (Unbuffered output)
74HCT.................High speed - CMOS - TTL inputs
74AHC.................Advanced - High speed - CMOS
74AHCT..............Advanced - High speed - CMOS - TTL inputs<
74FCT (-A,T,AT).Fast - CMOS - TTL inputs (speed variations)
74AC....................Advanced - CMOS
74ACT.................Advanced - CMOS - TTL inputs
74FACT................AC, ACT (Q) series
74ACQ.................Advanced - CMOS - Quiet outputs
74ACTQ...............Advanced - CMOS - TTL inputs - Quiet outputs
Bus Driver Families
74ABT.................Advanced - BiCMOS - Technology
74ABTE...............ABT - Enhanced Transceiver Logic
74ABTH..............Advanced - BiCMOS - Technology - bus Hold<
74BCT.................BiCMOS - TTL inputs
74BTL.................Backplane - Transceiver - Logic (BiCMOS)
74CBT.................Bus Switch
74CBTK..............CBT - Active Clamp
74FB....................Futurebus+
74GTL.................Gunning - Transceiver - Logic
74GTLP...............GTL - Plus
Low Voltage Families
74ALB.................Advanced - Low Voltage - BiCMOS
74LV (U)..............Low - Voltage (Unbuffered output) (CMOS)
74LVC (R) (U).....LV - CMOS (damping Resistor)(Unbuffered output)
74LVCH..............Low - Voltage - CMOS - bus Hold
74ALVC...............Advanced - Low - Voltage - CMOS
74LVT (R) (U)......LV - TTL (damping Resistor(Unbuffered output) (BiCMOS)
74LVTZ................Low - Voltage - TTL - High Impedance power-uup
74ALVC (R).........ALV - CMOS (bus Hold) (damping Resistor)
74ALVCH.............Advanced - Low - Voltage - CMOS - bus Hold>
74LCX..................LV - CMOS (operates with 3v and 5v suppliess)
74VCX..................LV - CMOS (operates with 1.8v and 3.6v suppplies
74CBTLV.............CBT - Low Voltage
3.) Karnaugh Mapping ( K-mapping )
Consider an n-dimensional hyper-cube, with two indices on a side, one index labelled "on", and one labelled "off". Thus, there are 2**n positions in the cube, each labelled with n "on"s or "off"s. Consider, an n-input boolean function; associate each of the inputs to the function with a different dimension of the hyper-cube. Now, there is a one-to-one association between the 2**n positions in the cube and the 2**n possible sets of input values to the function. Mark each position in the cube either "on" or "off" according to the result of the function when given the set of input values corresponding to that position. Now, this cube completely describes the function. As mentioned in the first section, a group of function can be specified by giving the sets of input values for which a function in the group must be "on" and also the sets of values for which it must be "off". This corresponds to partially filling out a function cube; some positions are marked either "on" or "off", and others are left unmarked. The goal in making the K-map of a function is to find an efficient way of expressing that function. When a group of functions is specified in the above way, it is because all of the functions in the group are equivalent for the input values that are given. Thus, the one function in the group that is most efficient to express can be chosen. This can be done by making a K-map from the partially filled-out cube for the group of functions. In K-mapping a single function, adjacent terms can be combined, because the new combined term still covers "on"s in the function. That is, they do not cover any of the "off"s in the cube; this is really what is important. In the partially-filled cube, terms can be combined so long as they do not cover "off"s; that is, they may be combined so as to cover the empty positions in the cube. The eventual result of K-mapping a partial cube expresses one particular function from the group of functions given by the cube. Moreover, it is the "best" function.