# vsim -Gwidth=8 -GAdd_width=8 work.spmem(spmem_v1) 
# Loading K:/MODELSIM/WIN32/../std.standard
# Loading K:/MODELSIM/WIN32/../ieee.std_logic_1164(body)
# Loading K:/MODELSIM/WIN32/../ieee.std_logic_arith(body)
# Loading K:/MODELSIM/WIN32/../ieee.std_logic_signed(body)
# Loading work.spmem(spmem_v1)
do K:/prj/spmem/sim/Vectors.do
# Copyright Jamil Khatib 1999 
# 
# This test vector file is an open design, you can redistribute it and/or 
# modify it under the terms of the Openip Hardware General Public 
# License as as published by the OpenIP organization and any 
# coming versions of this license. 
# You can check the draft license at 
# http://www.openip.org/oc/license.html 
# 
# 
# Creator : Jamil Khatib 
# Date 14/5/99 
# 
# version 0.19990704 
# contact me at khatib@ieee.org 
# .source
# .signals
# .wave
.wave.tree write -width 21.0cm -height 29.7cm -start {0 ns} -end {628 ns} -perpage {400 ns} -margin 1.0cm -pagecount 2 -selection visible -landscape wave_spmem_v1.ps
destroy .wave
