# vsim -sdftyp /=K:/prj/spmem/postsyn/time_sim.sdf -multisource_delay latest work.spmem 
# Loading K:/prj/spmem/postsyn/time_sim.sdf
# Loading K:/MODELSIM/WIN32/../std.standard
# Loading K:/MODELSIM/WIN32/../ieee.std_logic_1164(body)
# Loading K:/MODELSIM/WIN32/../std.textio(body)
# Loading K:/MODELSIM/WIN32/../ieee.vital_timing(body)
# Loading simprim.vcomponents
# Loading K:/MODELSIM/WIN32/../ieee.vital_primitives(body)
# Loading simprim.vpackage(body)
# Loading work.spmem(structure)
# Loading work.x_tri(x_tri_v)
# Loading work.x_buf(x_buf_v)
# Loading work.x_ff(x_ff_v)
# Loading work.x_one(x_one_v)
# Loading work.x_zero(x_zero_v)
# Loading work.x_or2(x_or2_v)
# Loading work.x_and4(x_and4_v)
# Loading work.x_or4(x_or4_v)
# Loading work.x_xor2(x_xor2_v)
# Loading work.x_and2(x_and2_v)
# Loading work.x_and6(x_and6_v)
# Loading work.x_inv(x_inv_v)
# Loading work.roc(roc_v)
do K:/prj/spmem/postsyn/Vectors.do
# Copyright Jamil Khatib 1999 
# 
# This test vector file is an open design, you can redistribute it and/or 
# modify it under the terms of the Openip Hardware General Public 
# License as as published by the OpenIP organization and any 
# coming versions of this license. 
# You can check the draft license at 
# http://www.openip.org/oc/license.html 
# 
# 
# Creator : Jamil Khatib 
# Date 14/5/99 
# 
# version 0.19990704 
# contact me at khatib@ieee.org 
# .source
# .signals
# .wave
destroy .wave
restart -f -nolist -nowave -nolog -nobreak
destroy .signals
# Loading K:/prj/spmem/postsyn/time_sim.sdf
destroy .source
do K:/prj/spmem/postsyn/VECTORS_10ns.DO
# Copyright Jamil Khatib 1999 
# 
# This test vector file is an open design, you can redistribute it and/or 
# modify it under the terms of the Openip Hardware General Public 
# License as as published by the OpenIP organization and any 
# coming versions of this license. 
# You can check the draft license at 
# http://www.openip.org/oc/license.html 
# 
# 
# Creator : Jamil Khatib 
# Date 14/5/99 
# 
# version 0.19990704 
# contact me at khatib@ieee.org 
# .source
# .signals
# .wave
restart -f -nolist -nowave -nolog -nobreak
# Loading K:/prj/spmem/postsyn/time_sim.sdf
destroy .wave
destroy .signals
destroy .source
do K:/prj/spmem/postsyn/VECTORS_10ns.DO
# Copyright Jamil Khatib 1999 
# 
# This test vector file is an open design, you can redistribute it and/or 
# modify it under the terms of the Openip Hardware General Public 
# License as as published by the OpenIP organization and any 
# coming versions of this license. 
# You can check the draft license at 
# http://www.openip.org/oc/license.html 
# 
# 
# Creator : Jamil Khatib 
# Date 14/5/99 
# 
# version 0.19990704 
# contact me at khatib@ieee.org 
# .source
# .signals
# .wave
destroy .wave
