Floating point numbers and calculations have great use in every day calculations like banks transactions, scientific calculations, graphics, egineering drawings and even games. These kind of calculations will be very solw if they are done without any hw support. This floating point unit core should deliver speed up the calculations. The hardware core and software libraries is going to be provided.
The main objective of this project is to build an IEEE-754 compatible Floating-point unit core and its software. This core should give high performance and have the ability to interface to any CPU core. The project should provide a set of small calculation units. The final step should use the fpu core in a stand alon floating point processor.
The core should be as an execution unit of the cpu or a co-processor.
The core should give exceptions to the CPU to store them.
The CPU must have the ability to mask and unmask the exceptions as described by the IEEE-754 standard. On the other hand, the FPU should generate the exceptions all time.
The FPU should provide a signal when the result is ready.
The CPU should provide a signal to load new instruction and operands.
The user should have the ability to read and mask the flags.
The flags should remain set as long as the software do not unset them.
The CPU should be interrupted upon any generation of unmasked exception.
The software should handle the flags to prevent frequent generation of interrupts and it also trap and handle all exceptions and modify the results upon the source of exception.
The interface between SW and HW depends on the used CPU and software platform. Instructions definitions should be easliy customizable. All FPU exceptions can derive external interrupt controller that provides interrupts to the CPU. The system should not be platform dependent.
three bits in the most right of the no. (Guard, round and sticky)
One complementer can be used and do a swap
Two exponent subtractions can be done e1-e2 and e2-e1 so as not to use a complement and to get a negative value
Invert the sign of the second operator in case of subtraction.
Calculates the difference between the two operands' exponents.
The diff is calculated using normal sign magnitude subtraction. ``This can be optimized by using a single complementer and perform a swaping for the negative number and check the small operand''
Check if the one of the operands is a special number (NaN or Infinity)
If NaN is one of the operands the result is NaN
If � check if the operation is �-� then NaN and Invalid exception is generated
The operands can be non-normalized and also the results
The system test bench should be composed of two parts. The data injection and checking part (called client later on) and the timing checking part (called server later on). This approach is seleced in order to have the ability to change the interface of the FPU and check it without the need to check the functionality of the system.
The software should generate test vectors for the test bench in acceptable readable format for the test bench in VHDL language.
It should generate numbers and operations randomly for the test bench.
It should to read mathematical formulae and generate sequence of numbers and operations to the test bench.
There should be a method to compare the results from the real calculations done on the CPU and from the fpu core.
All results from test bench and software should be in readable format with the ability to show all bit representations.
The software should have the ability to generate operations that give special numbers (infinity, zeros and NaN) and all kind of exceptions.
The software should know when the special numbers are going to be generated and not to calculate them using the normal software flow, else it will fail because the results will be handled by host traps.
